Stacked IC Package System with Exposed Lead Frame
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Solution Overview
Problem
There is a need for a stacked integrated circuit package system that offers multi-functionality, low package height, and low-cost manufacturing while addressing the challenges of defect density control, optical system resolution limits, and equipment availability in reducing feature size, particularly in the context of multi-die and package stacking for system-in-a-package integration.
Innovation Solution
The solution involves forming a lead and a die paddle from a lead frame, placing a second integrated circuit die over the first, connecting them, and encapsulating both with a portion of the lead and interconnects exposed, allowing for dual-side die-attach surfaces and hybrid interconnect configurations that minimize wire crossing and reduce electrical parasitics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If wafer manufacturing reduces transistor or capacitor feature size to increase circuit density, then circuit density and functionality are improved, but defect density control, optical system resolution limits, and availability of processing material and equipment become significant obstacles
Solution Approach 1:
The patent transitions from planar (2D) circuit integration to three-dimensional (3D) stacked integration. By stacking multiple dies vertically, the system achieves higher circuit density without further reducing feature size, thereby avoiding the manufacturing precision obstacles associated with sub-micron fabrication.
Solution Approach 2:
The patent implements package-in-package stacking where multiple integrated circuit dies are nested vertically within a single package. This nesting approach allows multiple functional blocks to be integrated in the vertical dimension, increasing overall system density without requiring smaller feature sizes on individual dies.
2Adaptability or versatility
If multi-die and package stacking are used to increase integration, then system functionality is enhanced, but package height increases
Solution Approach 1:
The patent merges multiple functional dies into a single integrated package structure. By combining logic dies, memory dies, and passive component carriers in a stacked configuration, the system achieves high functionality while maintaining a compact vertical profile through shared package infrastructure.
Solution Approach 2:
The patent creates a universal package platform that can accommodate multiple types of dies (logic, memory, passive components) in various stacking configurations. This multi-functional package design allows flexibility in system integration while maintaining controlled package height through standardized interconnect and encapsulation structures.
3Area of stationary object
If more integrated circuits are packed into smaller physical space, then space utilization is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent segments the integrated system into discrete, independently manufactured dies that are subsequently stacked. This segmentation allows each die to be optimized and manufactured separately using existing fabrication processes, reducing overall manufacturing complexity while achieving high density through vertical integration.
Solution Approach 2:
The patent performs preliminary actions by pre-assembling and testing individual dies before final package stacking. This modular approach allows for defect isolation, simplified rework, and reduced manufacturing complexity by breaking down the integration process into manageable stages rather than requiring complete system-level assembly.
Data Source
AI summary
A stacked integrated circuit package system is provided forming a lead and a die paddle from a lead frame, forming a first integrated circuit die having an interconnect provided thereon, placing a second integrated circuit die over the first integrated circuit die and the die paddle, connecting the second integrated circuit die and the lead, and encapsulating the first integrated circuit die and the second integrated circuit die with a portion of the lead and the interconnect exposed.