Stacked IC Package Interconnection Structure
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Solution Overview
Problem
Conventional IC packages, such as PBGA and FBGA, face challenges with large size, limited die size due to mold encapsulation, and mechanical stress, which are undesirable for mobile applications, and lack efficient interconnection methods for stacking overmolded packages.
Innovation Solution
The development of a package-to-package interconnection structure using truncated solder balls or conductive posts/pins that extend through the encapsulation material, allowing for direct die-to-package connections and enabling the stacking of IC packages with improved die size-to-substrate ratio and reduced mechanical stress, using thermally conductive epoxy and metal alloys like gold, copper, or silver.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional mold encapsulation is used to protect IC die and wirebonds, then reliability is improved, but package size increases and die size-to-package size ratio decreases
Solution Approach 1:
The patent extracts the encapsulation function from a separate mold compound layer and integrates it into the substrate itself. The substrate is configured with a first surface that contacts the IC die and wirebonds, and a second surface opposite the first surface, with the substrate material itself providing the encapsulation protection. This eliminates the need for a separate thick mold compound layer while maintaining protection of the IC components.
Solution Approach 2:
The patent merges the substrate structure with the encapsulation function. Instead of having a separate mold compound layer encapsulating the IC die and wirebonds, the substrate is designed to directly contact and protect these components. The substrate serves dual purposes: as the mounting platform for the IC die and as the encapsulation material protecting the wirebonds and die edges.
2Reliability
If thick mold compound is used for encapsulation, then protection is improved, but overall package profile height increases
Solution Approach 1:
The substrate is designed with sufficient thickness to provide both mechanical support and encapsulation protection. The first surface of the substrate contacts the IC die and wirebonds, while the substrate material itself forms the encapsulation barrier. This integration eliminates the need for an additional thick mold compound layer, thereby reducing the overall package profile height while maintaining adequate protection.
3Reliability
If mold cap is clamped to substrate for molding, then encapsulation is achieved, but die size is limited by mold cavity size
Solution Approach 1:
The patent removes the mold cap and mold cavity constraint from the packaging process. Instead of requiring a mold cap to be clamped to the substrate for encapsulation, the substrate itself is configured to provide the encapsulation function. This eliminates the mold cavity size limitation that previously constrained the maximum die size that could be packaged.
4Ease of operation
If periphery of substrate is left exposed for PBGA, then wirebond clearance is maintained, but package body size increases
Solution Approach 1:
The substrate is designed with sufficient lateral extent to provide both wirebond clearance and complete encapsulation. The first surface of the substrate contacts the IC die and wirebonds, providing the necessary clearance for wirebond operation. The substrate material extends laterally to enclose the IC components, eliminating the need for an exposed periphery while maintaining adequate wirebond clearance and reducing overall package size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the creation of compact, high-density IC packages with improved die size accommodation and reduced interconnect impedance, supporting high-speed signaling and broader bandwidth applications, while allowing for the stacking of various package types, including overmolded packages.
Implementation Method 1
An integrated circuit (IC) die is attached directly to a top surface of a substrate using a die attach material
Implementation Method 2
Wirebonds are used to electrically connect the integrated circuit of IC die to the printed circuit of substrate
Implementation Method 3
using thermally conductive epoxy
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3B
AI summary
Methods, systems, and apparatuses for integrated circuit (IC) package vertical interconnection are described herein. In an aspect of the invention, an IC package includes an IC die with contact pads. The IC package also includes interconnect members which are coupled to the die at the contact pads. An encapsulating material encapsulates the IC die and the interconnect members such that a contact surface of each interconnect member is accessible at a surface of the encapsulating material. A second IC package is coupled to the first IC package through the plurality of interconnect members of the first IC package. In an example, solder balls attached to a bottom of the second IC package are coupled to the contact surfaces of the interconnect members to couple the first IC package and the second IC package.