Stacked IC Package Layout for Stress and Delamination Control

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The semiconductor industry faces challenges in creating smaller and more efficient packaging techniques for semiconductor dies due to stress and delamination issues at the interface between integrated circuit dies, which can lead to warpage and reduced integration density.

Innovation Solution

The integration circuit package design incorporates a lateral offset between the sidewalls of upper and lower dies, using dielectric and gap-filling materials to reduce stress and prevent delamination, with a multi-layered dielectric liner structure to manage thermal expansion differences.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If semiconductor dies are stacked closely together to increase integration density, then the quantity of components per unit area increases, but stress and delamination occur at the die interface leading to warpage

Engineering Contradiction:

Improveintegration densityVSAvoidpackage integrity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by forming a liner layer and gap-filling material around the first die before attaching the second die. This pre-structure preparation creates a stress-managed interface that prevents delamination and warpage when the second die is subsequently attached, thereby maintaining package integrity while achieving high integration density through close stacking.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If the lateral offset between dies is reduced to maximize space utilization, then integration density improves, but stress concentration increases leading to delamination

Engineering Contradiction:

Improveintegration densityVSAvoidinterface stress

Core Design Contradiction:

ProductivityVSStress or pressure

Solution Approach 1:

The patent introduces a liner layer and gap-filling material as intermediary structures between the first and second dies. These intermediary layers act as stress buffers that reduce stress concentration at the die interface, allowing the lateral offset to be minimized for high integration density without causing delamination.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If different materials are used to manage thermal expansion differences, then thermal stress is reduced, but device complexity increases

Engineering Contradiction:

Improvethermal stress managementVSAvoidmulti-layered structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by carefully selecting materials with specific thermal expansion coefficients for the liner layer and gap-filling material. These material parameters are chosen to match or complement the thermal properties of the semiconductor dies, thereby reducing thermal stress during temperature variations while maintaining a relatively simple two-layer structural complexity.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20250349692A1Integrated circuit package and methods of forming the same

Publication Date: 2025.11.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A device includes: a first integrated circuit (IC) die; a first dielectric material around first sidewalls of the first IC die; a second IC die over and electrically coupled to the first IC die; and a second dielectric material over the first dielectric material and around second sidewalls of the second IC die, where in a top view, the second sidewalls of the second IC die are disposed within, and are spaced apart from, the first sidewalls of the first IC die.