Stacked IC Package with Mold Cap for High Density
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Solution Overview
Problem
Current integrated circuit packaging technologies face challenges in increasing semiconductor die density, reliability, and manufacturing yield, particularly due to limitations in compact design, testing of individual die before assembly, and inefficiencies in using known-good-die (KGD) in multi-chip modules.
Innovation Solution
The integrated circuit leaded stacked package system combines an extended-lead integrated circuit package with a no-lead package, using a mold cap and package-stacking layer to provide electrical interconnectivity and allow for testing of individual dies before assembly, thereby ensuring known-good packages and improving yield and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple IC devices are packaged side by side in a horizontal layer, then the packaging can accommodate multiple devices, but the board space is consumed inefficiently and device density is limited
Solution Approach 1:
The patent transitions from horizontal side-by-side packaging to vertical stacked packaging, utilizing the third dimension (height) to accommodate multiple IC devices. This dimensional change allows multiple devices to be packaged within a smaller footprint area, effectively increasing device density while reducing board space consumption.
2Reliability
If individual IC devices are tested before assembly, then manufacturing yield can be improved through known-good-die selection, but the testing process becomes more complex and time-consuming
Solution Approach 1:
The patent divides the testing process into two stages: individual die testing before assembly, and package-level testing after assembly. This segmentation allows for known-good-die selection to improve yield while managing testing complexity through systematic organization of test procedures at different hierarchical levels.
Solution Approach 2:
The patent implements preliminary testing of individual IC devices before they are assembled into packages. This preliminary action ensures that only known-good-die are selected for assembly, improving manufacturing yield by preventing defective devices from being incorporated into final products.
3Area of stationary object
If IC devices are packaged in a compact stacked configuration, then board space is reduced and density increases, but manufacturing and assembly processes become more difficult
Solution Approach 1:
The patent employs a nested packaging structure where multiple IC devices are stacked vertically within a common package housing. This nesting arrangement achieves compact footprint while maintaining ease of manufacture by treating the stacked assembly as a single integrated unit that can be handled and installed as one component.
Solution Approach 2:
The patent introduces an intermediary substrate or carrier that facilitates the stacking and interconnection of multiple IC devices. This intermediary component simplifies the manufacturing process by providing a platform for precise alignment and connection, making the complex stacked configuration easier to manufacture and assemble.
Data Source
AI summary
An integrated circuit leaded stacked package system includes forming a no-lead integrated circuit package having a mold cap, and attaching a mold cap of an extended-lead integrated circuit package facing the mold cap of the no-lead integrated circuit package.