Stacked IC Package Layout for Die Interface Stress Relief
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing stress at the interface between integrated circuit dies in packaging, leading to issues like delamination and warpage due to differences in thermal expansion coefficients, especially when dies are closely aligned or overhang each other.
Innovation Solution
The implementation of a lateral offset between the sidewalls of upper and lower dies, along with the use of dielectric liners and gap-filling materials, helps to reduce stress and prevent delamination and warpage by ensuring the upper dies are disposed within and spaced apart from the boundary defined by the lower dies, and the use of conductive vias and bonding films for electrical coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dies are closely aligned or overhang each other to improve integration density, then more components can be integrated into a given area, but stress at the interface increases leading to delamination and warpage
Solution Approach 1:
The patent introduces an intermediary structure (dielectric material filling the laterally offset space between dies) to mediate the interface between closely aligned dies. This intermediary reduces stress concentration at the die interface while maintaining high integration density, preventing delamination and warpage without sacrificing productivity.
Solution Approach 2:
The patent employs asymmetric positioning of dies with lateral offset rather than perfect alignment or overhang. This asymmetric arrangement creates a controlled geometry where the second die is offset relative to the first die, reducing stress at the interface while still achieving high integration density through vertical stacking.
2Reliability
If lateral offset is introduced between dies to reduce stress and prevent delamination, then interface stability improves, but manufacturing complexity increases
Solution Approach 1:
The patent resolves the manufacturing complexity issue by transitioning from two-dimensional planar alignment to three-dimensional positioning with lateral offset. The dielectric material fills the laterally offset space, creating a stress-relief structure that improves interface stability while the offset geometry can be integrated into existing 3D packaging processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the likelihood of delamination and warpage in integrated circuit packages by managing stress at the interface and improving the structural integrity of the package, while also enhancing heat dissipation through the use of conductive vias and bonding films.
Implementation Method 1
The implementation of a lateral offset between the sidewalls of upper and lower dies, along with the use of dielectric liners and gap-filling materials, helps to reduce stress and prevent delamination and warpage
Implementation Method 2
enhancing heat dissipation through the use of conductive vias and bonding films
Data Source
AI summary
A device includes: a first integrated circuit (IC) die; a first dielectric material around first sidewalls of the first IC die; a second IC die over and electrically coupled to the first IC die; and a second dielectric material over the first dielectric material and around second sidewalls of the second IC die, where in a top view, the second sidewalls of the second IC die are disposed within, and are spaced apart from, the first sidewalls of the first IC die.