Stacked IC Redistribution Lines for Dense Low-Parasitic Interconnects
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving higher integration density, smaller form factors, cost-effectiveness, and lower power consumption, which existing technologies struggle to address through conventional packaging techniques for stacked semiconductor devices.
Innovation Solution
The implementation of a package with stacked dies and an interconnect structure using metal hard masks or redistribution lines (RDLs) that form conductive plugs and redistribution lines to connect semiconductor chips, allowing for efficient electrical coupling and signal routing between stacked semiconductor wafers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional packaging techniques are used for stacked semiconductor devices, then manufacturing simplicity is maintained, but integration density and form factor reduction are limited
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional stacked architecture, where multiple semiconductor dies are vertically arranged and interconnected through through-silicon vias (TSVs). This dimensional change enables higher integration density by utilizing the vertical space rather than expanding the horizontal footprint, directly resolving the contradiction between integration density and packaging complexity.
Solution Approach 2:
The patent implements nested interconnect structures where redistribution layers and conductive plugs are embedded within the semiconductor substrate layers. Multiple functional layers are nested vertically, with each layer containing conductive elements that interconnect to form complex three-dimensional circuits, enabling high integration density while maintaining manufacturability through systematic layering.
2Volume of moving object
If semiconductor wafers are stacked to reduce form factor, then device size is reduced, but parasitic interference increases
Solution Approach 1:
The patent applies different material properties and structural characteristics to different regions of the stacked device. Specifically, conductive plugs are strategically placed and dimensioned to provide electrical connectivity while minimizing parasitic inductance and resistance. The redistribution layers are designed with optimized trace widths and spacing to reduce crosstalk and electromagnetic interference, thereby reducing parasitic effects while maintaining compact form factor.
Solution Approach 2:
The patent introduces intermediate redistribution layers and shielding structures between stacked semiconductor dies to act as mediators that isolate and reduce parasitic interference. These intermediate layers provide electrical isolation and signal routing that prevents harmful electromagnetic coupling between adjacent dies, enabling compact stacking while maintaining signal integrity.
3Reliability
If more conductive paths are added for better signal routing, then electrical connectivity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the interconnect structure into discrete functional units: through-silicon vias for vertical connectivity, redistribution layers for lateral signal routing, and bonding pads for die-to-die connection. Each segment performs a specific function and can be manufactured using standardized processes, enabling complex three-dimensional connectivity while maintaining manufacturing simplicity through modular construction.
Solution Approach 2:
The patent designs the interconnect structure with universal elements that serve multiple functions. The redistribution layers simultaneously provide signal routing, power distribution, and ground reference planes. The conductive plugs serve both as mechanical anchors for die attachment and as electrical interconnects, reducing the number of separate components needed and simplifying manufacturing while achieving reliable electrical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher integration density, reduced form factor, cost-effectiveness, and lower power consumption by providing continuous conductive paths and improved signal routing between stacked semiconductor chips, while minimizing parasitic interference.
Implementation Method 1
A conductive plug is underlying and electrically coupled to the redistribution line. The conductive plug includes a first portion extending from a top surface of the first substrate to a bottom surface of the first substrate, and a second portion extending from the bottom surface of the first substrate to the metal pad.
Data Source
AI summary
A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.