Stacked IC Package with Recessed Sidewalls
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Solution Overview
Problem
The existing methods for packaging integrated circuits are complex and costly due to the need for precise interconnection of stacked circuits, which requires forming conductive vias through multiple semiconductor layers and wiring layers, and current techniques do not efficiently reduce the complexity and cost of this process.
Innovation Solution
The method involves stacking integrated circuits with the formation of conductive vias that extend through both semiconductor and wiring layers, followed by filling these vias with conductive material to electrically contact input/output pads, and using selective etching and low-temperature plasma oxide deposition to create insulating layers, allowing for direct bonding without glue layers and reducing fabrication complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive vias are formed through multiple semiconductor layers and wiring layers using existing methods, then electrical connectivity between stacked integrated circuits is achieved, but the fabrication process becomes complex and costly
Solution Approach 1:
The fabrication process is divided into distinct stages: first forming vias through semiconductor layers, then forming vias through wiring layers, and finally filling with conductive material. This segmentation allows each stage to be optimized independently, reducing overall process complexity while maintaining electrical connectivity reliability.
Solution Approach 2:
The patent performs preliminary actions by forming via holes and applying insulating layers before final conductive material deposition. This preliminary preparation simplifies the subsequent filling process and ensures proper electrical isolation, reducing the complexity of the overall fabrication sequence.
2Reliability
If precise interconnection of stacked circuits is implemented through conventional via formation techniques, then electrical connectivity is achieved, but manufacturing cost increases
Solution Approach 1:
The patent merges the via formation process with the existing semiconductor fabrication workflow, utilizing standard photolithography and etching techniques that are already integrated into production lines. This consolidation avoids the need for specialized equipment or processes, thereby reducing manufacturing costs while achieving precise electrical interconnections.
Solution Approach 2:
The invention adjusts process parameters such as via diameter, depth, and filling material composition to optimize for cost-effective manufacturing. By tuning these parameters within standard process capabilities, the patent achieves reliable electrical connectivity without requiring expensive advanced fabrication techniques.
3Reliability
If multiple fabrication steps are used to form conductive vias through stacked integrated circuits, then electrical connectivity is achieved, but fabrication time increases
Solution Approach 1:
The patent maintains continuity of useful action by performing via formation, insulating layer deposition, and conductive material filling in a continuous sequence without intermediate processing steps. This continuous fabrication approach minimizes cycle time and maximizes productivity while ensuring reliable electrical connectivity through the stacked integrated circuits.
Solution Approach 2:
Preliminary formation of via holes and insulating layers is performed in advance, allowing the final conductive material filling to proceed rapidly. This preliminary preparation eliminates the need for time-consuming adjustments during the filling stage, thereby accelerating the overall fabrication process while maintaining connection reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process by reducing the complexity and cost of forming conductive vias, enabling efficient electrical connectivity between stacked integrated circuits while maintaining high integration density and performance.
Implementation Method 1
forming an insulating layer on the recessed sidewalls of the semiconductor layer by low-temperature plasma oxide deposition
Implementation Method 2
a conductive via extends through the plurality of integrated circuits including through the semiconductor layers and through the wiring layers thereof, wherein the conductive via selectively electrically contacts the wiring
Data Source
AI summary
Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages are also described.