Stacked IC Routing Wire Layout for Dense, Short-Resistant Wiring
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Solution Overview
Problem
Stacked integrated devices face challenges with reduced wire area leading to potential interference or electrical shorts between wires, limiting their integration density and performance.
Innovation Solution
The design includes a lower and upper transistor region with specific source/drain and gate structures, along with routing wires that are strategically positioned to increase the width and spacing of input and output wires, reducing interference and shorts by being formed at different levels relative to the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacked integrated devices are used to achieve high integration density, then the integration density is improved, but the area for wires is reduced leading to interference or electrical shorts between wires
Solution Approach 1:
The patent introduces a vertical dimension by forming routing wires at different heights (first level and second level) relative to the substrate. This multi-level wire architecture allows signals to be routed at different vertical planes, effectively increasing the available wiring space without expanding the horizontal footprint, thus resolving the contradiction between high integration density and wire reliability
Solution Approach 2:
The wiring system is segmented into multiple levels with routing wires formed at a first level and input/output wires formed at a second level. This segmentation separates different signal paths vertically, reducing the probability of interference and electrical shorts while maintaining high integration density
2Reliability
If wire spacing is increased to reduce interference and electrical shorts, then wire reliability is improved, but the available area for routing is reduced
Solution Approach 1:
By utilizing the vertical dimension to form routing wires at multiple levels (first level closer to substrate, second level farther from substrate), the patent increases effective wiring capacity without requiring additional horizontal space. This allows adequate spacing between wires at each level while maintaining compact overall device area
Solution Approach 2:
The patent implements a nested wire structure where routing wires at the first level are positioned beneath input and output wires at the second level. This nested arrangement allows efficient use of vertical space, enabling increased wire spacing at each level while maintaining compact routing area
Data Source
AI summary
Integrated circuit devices including standard cells are provided. The integrated devices may include a lower transistor region and an upper transistor region. The lower transistor region may include a lower active region, lower source/drain regions, and lower gate structures arranged alternately with the lower source/drain regions. The upper transistor region may include an upper active region, upper source/drain regions, and upper gate structures arranged alternately with the upper source/drain regions. The upper gate structures may include a first upper gate structure. The integrated devices may also include an input wire, an input via electrically connecting the input wire to the first upper gate structure, and a routing wire electrically connecting a pair of the lower source/drain regions or a pair of the upper source/drain regions. An upper surface of the routing wire may be closer to the substrate than an upper surface of the input wire.