3D Stacked IC Interconnect Layers for Shorter Signal Routing
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Solution Overview
Problem
As we approach the limits of transistor density on semiconductor substrates, there is a need for innovative methods to increase the number of transistors on an IC chip beyond what is currently possible, as predicted by the end of Moore's Law.
Innovation Solution
A three-dimensional (3D) circuit is formed by stacking two or more integrated circuit (IC) dies to share interconnect layers that distribute power, clock, and data-bus signals, utilizing direct bonding techniques such as DBI to establish a large number of direct connections between the top interconnect layers, allowing for orthogonal wiring directions that reduce capacitive load and increase the density of connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more interconnect layers are added to increase transistor density, then the number of transistors that can be defined increases, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from traditional two-dimensional planar interconnect layers to three-dimensional stacked interconnect layers. Multiple interconnect layers are stacked vertically to provide additional routing dimensions, allowing signals to travel between stacked IC dies through vertical vias and interconnect structures, thereby increasing transistor density without proportionally increasing manufacturing complexity
Solution Approach 2:
The patent implements nested interconnect structures where lower-level interconnect layers are embedded within or surrounded by upper-level interconnect layers. The lower-level interconnect layers provide foundational routing while upper-level layers provide additional routing capacity, creating a hierarchical nested structure that efficiently utilizes vertical space to increase transistor density
2Quantity of substance
If more interconnect layers are added to increase transistor density, then the number of transistors that can be defined increases, but the manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates preliminary alignment features and registration structures during the fabrication process of stacked IC dies. Alignment marks and registration vias are pre-defined in lower-level interconnect layers to guide the precise positioning and bonding of upper-level interconnect layers, ensuring accurate alignment without requiring excessive manufacturing precision
Solution Approach 2:
The patent introduces intermediary alignment structures and bonding interfaces between stacked interconnect layers. These intermediary elements serve as mediators that facilitate precise alignment during the stacking process, reducing the overall precision requirements by breaking down the alignment task into manageable steps between adjacent layers
3Ease of manufacture
If traditional two-dimensional IC designs are used, then manufacturing is simpler, but the number of transistors that can be defined is limited
Solution Approach 1:
The patent extends traditional two-dimensional IC design into three dimensions by stacking multiple IC dies vertically. This dimensional transition allows signals to travel between stacked dies through vertical interconnect structures, effectively multiplying the transistor capacity while maintaining manufacturing processes that are extensions of conventional two-dimensional fabrication techniques
4Quantity of substance
If signal paths are lengthened to accommodate more transistors, then more transistors can be defined, but signal routing performance deteriorates
Solution Approach 1:
The patent utilizes vertical stacking to create short direct signal paths between adjacent interconnect layers through vertical vias and interconnect structures. This three-dimensional routing approach replaces long horizontal signal paths with short vertical paths, maintaining high signal routing speed while accommodating increased transistor density through additional vertical routing dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of interconnect layers required, optimizes space by sharing power and clock circuits, and enables higher performance and lower costs by providing shorter signal paths and better signal routing, thus overcoming the limitations of traditional two-dimensional IC designs.
Implementation Method 1
the top interconnect layers bonded to each other through a direct bonding process that establishes direct-contact metal-to-metal bonding
Data Source
AI summary
Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.