Stacked IC Testing via Through-Silicon Vias
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Solution Overview
Problem
Current testing methods for stacked integrated circuit devices are inefficient in detecting faults in both functional logic and memory across multiple dies, particularly in highly embedded processor circuitry, due to limitations in existing scan chain and memory built-in self-test techniques.
Innovation Solution
A method and device configuration that utilize through-silicon vias to send testing control signals between dies, enabling comprehensive testing of functional logic and memory on both the first and second dies, with testing logic on one die controlling and coordinating tests on both, including scan chain testing and memory built-in self-test (MBIST) operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate testing methods (scan chain for logic, MBIST for memory) are used independently on each die, then testing coverage for individual components is achieved, but fault detection efficiency across the stacked device is reduced
Solution Approach 1:
The patent combines scan chain testing and MBIST operations into a unified testing framework where a single testing controller coordinates both testing methods across multiple dies simultaneously. The testing apparatus integrates logic testing and memory testing functions, allowing comprehensive fault detection across the stacked device without requiring separate independent testing processes for each component.
Solution Approach 2:
The testing controller is designed with multi-functionality to perform both scan chain testing for logic circuits and MBIST for memory structures. This universal testing apparatus can adapt its operation mode based on the target component being tested, eliminating the need for separate dedicated testing equipment for different component types and improving overall testing efficiency.
2Reliability
If comprehensive testing of both functional logic and memory on multiple dies is performed, then fault detection coverage is improved, but testing complexity increases
Solution Approach 1:
The testing controller acts as an intermediary that manages the complexity of coordinated testing across multiple dies. It handles the coordination between different testing methods (scan chain and MBIST), manages test pattern distribution, and consolidates test results from various dies and component types. This centralized control mechanism simplifies the overall testing process despite the multiple components being tested simultaneously.
3Ease of operation
If through-silicon vias are used to send testing control signals between dies, then coordinated testing across dies is enabled, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes through-silicon vias to establish vertical communication pathways between stacked dies, transitioning from traditional planar signal transmission to three-dimensional vertical interconnection. This dimensional change enables efficient control signal transmission across multiple die layers, facilitating coordinated testing operations without requiring complex lateral routing through the substrate.
Data Source
AI summary
A method for testing a stacked integrated circuit device comprising a first die and a second die, the method comprising: sending from testing logic of the first die, first testing control signals to first testing apparatus on the first die; in response to the first testing control signals, the first testing apparatus running a first one or more tests for testing functional logic or memory of the first die; sending from the testing logic of the first die, second testing control signals to the second die via through silicon vias formed in a substrate of the first die; and in dependence upon the second testing control signals from the first die, running a second one or more tests for testing the stacked integrated circuit device.