Stacked IC Redistribution Lines With Through-Wafer Conductive Plugs
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to achieve higher integration density, smaller form factors, and lower power consumption while maintaining effective electrical connectivity between stacked semiconductor wafers.
Innovation Solution
The formation of continuous conductive plugs and redistribution lines (RDLs) that penetrate through semiconductor wafers, providing direct electrical connections between stacked chips, reducing the physical size and power consumption, and minimizing parasitic interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bonding techniques are used to bond semiconductor wafers, then the wafers can be connected, but the electrical connectivity and signal routing between stacked wafers become complex and less efficient
Solution Approach 1:
The patent transitions from planar signal routing to three-dimensional vertical routing by forming conductive plugs that extend through dielectric layers and metal layers in the vertical dimension. This allows direct electrical connections between stacked semiconductor wafers, reducing routing complexity while improving connectivity reliability.
Solution Approach 2:
The patent implements a nested interconnect structure where conductive plugs are embedded within dielectric layers and metal layers, which are themselves nested within the semiconductor wafer stack. This nested arrangement enables efficient vertical signal routing through multiple layers while maintaining compact packaging.
2Quantity of substance
If more components are integrated into a given area by reducing minimum feature size, then integration density improves, but manufacturing complexity and power consumption increase
Solution Approach 1:
The patent moves from two-dimensional lateral integration to three-dimensional vertical integration by stacking semiconductor wafers and providing direct vertical electrical connections through conductive plugs. This reduces the need for extensive lateral routing, thereby reducing power consumption while maintaining high integration density.
3Volume of moving object
If stacked semiconductor wafers are bonded together to reduce form factor, then device size decreases, but ensuring effective electrical connectivity between wafers becomes more challenging
Solution Approach 1:
The patent forms conductive plugs and establishes electrical interconnections between stacked wafers before final packaging. This preliminary action ensures reliable electrical connectivity is established while the wafers are still accessible, facilitating effective bonding and connection in the stacked configuration.
Solution Approach 2:
The patent replaces mechanical wire bonding or tab connections with direct conductive plug connections formed through the dielectric and metal layers. This substitution provides more reliable and compact electrical connectivity between stacked wafers, enabling reduced form factor while maintaining connection integrity.
Data Source
AI summary
A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.