Vertically Stacked IC Dies With Voltage Domain Stacking
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Solution Overview
Problem
Current packaging architectures for integrated circuits (ICs) in Multi-Chip Modules (MCMs) are limited in their ability to scale to next-generation servers due to bandwidth reduction, signal delay, and signal distortion, particularly when dealing with high-speed signal speeds and data rates, and face challenges in power delivery to vertically stacked IC dies with dense power circuitry.
Innovation Solution
The implementation of vertically stacked IC dies with lateral edges, coupled through a voltage converter, using interconnects that allow for serial power delivery and reduced current requirements, enabling efficient power delivery and signal speed while minimizing package complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional packaging architectures are used for vertically stacked IC dies, then power delivery is challenging, but device complexity increases
Solution Approach 1:
The patent transitions from traditional planar power delivery to three-dimensional voltage domain stacking, where multiple voltage domains are stacked vertically. This allows power delivery to scale with the stacked architecture while maintaining manageable complexity through systematic organization of voltage domains across multiple layers.
Solution Approach 2:
The patent divides the power delivery system into multiple independent voltage domains, each serving specific functional blocks. This segmentation allows independent optimization of power delivery to different regions and reduces the complexity of managing power across the entire stacked structure by breaking it into manageable domains.
2Speed
If vertically stacked IC dies are implemented, then signal speed should improve, but bandwidth reduction and signal distortion occur
Solution Approach 1:
The patent introduces intermediate voltage domains and buffer structures between stacked dies to mediate signal transmission. These intermediaries help maintain signal integrity by providing controlled impedance transitions and reducing reflections, thereby preventing bandwidth reduction and signal distortion while preserving the speed benefits of vertical stacking.
3Power
If current power delivery methods are used for vertically stacked dies, then current requirements increase, but power delivery efficiency decreases
Solution Approach 1:
The patent changes the voltage parameter across different stacked layers, implementing higher voltage domains at certain levels and lower voltage domains at others. This parameter change allows power delivery to be optimized for each layer's specific requirements, reducing overall current requirements while improving power delivery efficiency through matched impedance and reduced resistive losses.
Data Source
Figure 1~2
Figure 3A~3B
Figure 3C~3D
AI summary
Embodiments of an integrated circuit (IC) die may include a substrate having a first surface with an array of first conductive pads, an opposite second surface, a third surface orthogonal to first and second surfaces, and through substrate vias (TSVs) electrically coupled to the array of first conductive pads; and a metallization stack having a fourth surface, an opposite fifth surface, and a sixth surface orthogonal to the fourth and fifth surfaces, and including a conductive trace parallel to the fourth and fifth surfaces and exposed at the sixth surface, and conductive vias between the fourth and fifth surfaces and exposed at the fifth surface, wherein the second surface of the substrate is coupled to the fourth surface of the metallization stack and an interface between the substrate and the metallization stack includes an array of second conductive pads electrically coupled to the conductive trace and conductive vias.