Stacked IC Die Package CTE Balancing for Warpage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuit (IC) dies experience warpage due to differences in coefficients of thermal expansion (CTE) among materials, which can impair electronic performance, especially in stacked IC dies or chiplets.
Innovation Solution
The electronic device includes a substrate with a first CTE, an IC die with first and second metal layers having different thicknesses and CTEs, and a dielectric layer with a third CTE that induces stresses to compensate for warpage, thereby maintaining device flatness and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the uppermost levels of metal layers is increased, then the electronic performance is improved, but the warpage is exacerbated
Solution Approach 1:
The patent introduces a dielectric layer with specifically engineered CTE parameters to counterbalance the thermal expansion effects of metal layers. By selecting a dielectric material whose CTE is lower than both the substrate and metal layers, the system achieves stress compensation that maintains both electrical performance and dimensional stability across temperature variations.
Solution Approach 2:
The patent creates a composite structure comprising multiple layers with different CTE characteristics (substrate, metal layers, and dielectric layer). This composite arrangement allows the components to work together, where the dielectric layer's lower CTE compensates for the higher CTE of metal layers, reducing overall warpage while maintaining the necessary electrical connectivity and performance.
2Shape
If the thickness of the uppermost levels of metal layers is reduced, then the warpage is mitigated, but the voltage drop increases
Solution Approach 1:
The dielectric layer acts as an intermediary stress-compensating element between the substrate and metal layers. By positioning this layer strategically, it mediates the thermal stress interactions, allowing the metal layers to maintain optimal thickness for electrical performance while the dielectric layer absorbs and compensates for the resulting warpage through its differential CTE.
3Reliability
If multiple materials with different CTEs are used in the IC die, then the functional performance is improved, but the warpage increases in response to temperature changes
Solution Approach 1:
The patent applies local quality by introducing a dielectric layer with specifically tailored CTE properties at a particular location in the stack (between the substrate and metal layers). This localized material selection creates a stress-compensating region that addresses the warpage issue without compromising the overall functional performance enabled by the multi-material construction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively mitigates warpage in IC dies by balancing stresses induced by metal layers and dielectric layers, improving the flatness and electronic performance of the device across a range of temperatures.
Implementation Method 1
Each of the above materials (semiconductor, dielectric, and metal) has a different coefficient of thermal expansion (CTE)... in response to temperature changes, the IC die may become warped due to the difference in CTEs
Implementation Method 2
the dielectric layer being configured to induce at least in the substrate, in response to the increase in the temperature, a second stress that compensates for at least part of the warpage
Data Source
AI summary
An electronic device includes (i) a substrate having a first coefficient of thermal expansion (CTE), (ii) an integrated circuit (IC) die formed on the substrate and including first metal layers having a first thickness, and second metal layers having a second thickness, greater than the first thickness, the second metal layers have a second CTE, greater than the first CTE, the first and second metal layers are configured to induce, in response to an increase in a temperature of the electronic device, a first stress that acts to cause a warpage at least in the substrate, and (iii) a dielectric layer having a third CTE less than the first and second CTEs, is (a) disposed on the second metal layers, and (b) configured to induce at least in the substrate, in response to the increase in the temperature, a second stress that compensates for at least part of the warpage.