Stacked III-V Semiconductor Diode for High-Blocking Voltage
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Solution Overview
Problem
Conventional high-blocking diodes made of Si or SiC struggle to achieve high switching frequencies and current densities with low on-resistance and capacitance, while being cost-effective and thermally stable.
Innovation Solution
A stacked III-V semiconductor diode with a p+ GaAs substrate, an n- layer, and an n+ layer, featuring an intermediate n-doped layer with a different dopant concentration, allowing for blocking voltages from 200V to 3,300V with reduced on-resistance and capacitance, and enabling production at lower costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional high-blocking diodes are made of Si or SiC, then blocking voltage is achieved, but on-resistance and capacitance are high, limiting switching frequency and current density
Solution Approach 1:
The patent changes the material parameter from conventional Si or SiC to III-V compound semiconductor (GaAs-based), which fundamentally alters the electrical characteristics. This material parameter change enables simultaneous achievement of high blocking voltage (200V-3,300V), low on-resistance, and low capacitance, thereby resolving the contradiction between reliability and productivity
Solution Approach 2:
The patent employs a composite structure with multiple doped layers (p+ substrate, n- layer, n+ layer, and intermediate layer with graded dopant concentration) within the III-V compound material system. This composite layer structure optimizes both blocking voltage capability and switching performance by distributing electrical stress and controlling carrier behavior across different regions
2Reliability
If conventional high-blocking diodes are made of SiC, then high blocking voltage is achieved, but production cost increases
Solution Approach 1:
The patent substitutes the expensive SiC material with a more cost-effective III-V compound semiconductor material system. By using GaAs-based materials that are generally more economical to produce while still achieving the required blocking voltage performance, the patent reduces production costs without sacrificing reliability
Solution Approach 2:
The patent changes the material composition parameter from SiC to III-V compound, which offers a more favorable cost-performance ratio. This parameter change maintains the necessary blocking voltage capability while significantly improving ease of manufacture and reducing production costs
3Productivity
If conventional diodes operate at high switching frequencies, then productivity increases, but on-resistance and capacitance must be reduced
Solution Approach 1:
The patent changes the fundamental material parameter to III-V compound semiconductor, which intrinsically provides lower capacitance and on-resistance compared to conventional materials. This parameter change enables high switching frequencies (30 kHz to 0.5 GHz) without requiring complex circuit designs to compensate for high losses
Solution Approach 2:
The patent introduces a vertical dimension with multiple stacked doped layers (p+ substrate, n- layer, n+ layer, and intermediate layer), creating a three-dimensional structure that optimizes electrical properties. This layered architecture reduces both on-resistance and capacitance by distributing electrical stress and controlling carrier transport across multiple interfaces and regions
Data Source
Figure 1~4
AI summary
Stacked III-V semiconductor diode (10) comprising a p+ substrate (12) with a dopant concentration of 5*1018-5*1020 cm-3, a layer thickness (Ds) of 50-500 µm and comprising a GaAs compound, an n- layer (16) with a dopant concentration of 1014-1016 cm-3, a layer thickness (D1) of 10-300 µm and comprising a GaAs compound, an n+ layer (18) with a dopant concentration of at least 1019 cm-3, a layer thickness (D2) of less than 2 µm and comprising a GaAs compound, wherein the n- layer (16) and the n+ layer (18) are metallurgically bonded to each other, and a doped layer is located between the p+ substrate (12) and the n- layer (16). The intermediate layer (14) has a layer thickness (Dp) of 5-50 µm and a dopant concentration of 1015-1017 cm-3 and is connected to the p+ substrate (12) and to the n- layer (16) in a metallurgically bonded manner.