Stacked Peripheral Circuit ILD Layout for 3D Memory Density
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Solution Overview
Problem
As the number of word lines stacked in 3D non-volatile memory devices increases, the area occupied by the peripheral circuit region relative to the cell region increases, leading to reduced space utilization and constrained design of highly integrated memory devices.
Innovation Solution
The memory device incorporates two or more overlapping peripheral circuit regions with varying thicknesses of lowermost inter-layer dielectric (ILD) regions, optimizing the arrangement of high-speed and high-voltage circuits on different layers to improve performance and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines stacked in 3D non-volatile memory devices increases, then the capacity and integration of the memory device increase, but the percentage of area occupied by the peripheral circuit region increases, leading to reduced space utilization
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration by forming peripheral circuit regions at different heights above the substrate. Multiple peripheral circuit regions are vertically stacked and overlap when viewed in plan view, allowing circuits to be arranged in the vertical dimension rather than consuming additional horizontal area.
Solution Approach 2:
The patent implements nested peripheral circuit regions where one peripheral circuit region is positioned within the vertical projection of another peripheral circuit region. This nesting arrangement allows multiple circuit regions to occupy overlapping footprints, effectively reducing the total area required for peripheral circuits while maintaining all necessary circuit functions.
2Area of stationary object
If peripheral circuit regions are stacked vertically to improve space utilization, then area efficiency increases, but circuit performance may be compromised due to uniform thickness constraints
Solution Approach 1:
The patent applies different thicknesses to different lowermost inter-layer dielectric regions corresponding to different peripheral circuit regions. Specifically, the first peripheral circuit region has a first lowermost ILD region with a first thickness, while the second peripheral circuit region has a second lowermost ILD region with a second thickness different from the first. This local differentiation allows optimization of circuit performance for different functional requirements within the stacked structure.
Solution Approach 2:
The patent changes the thickness parameter of the lowermost inter-layer dielectric regions to optimize circuit performance. By varying the thickness of the lowermost ILD region across different peripheral circuit regions, the patent enables tailored electrical characteristics and performance optimization for high-speed circuits versus high-voltage circuits while maintaining vertical stacking for space efficiency.
Data Source
AI summary
A memory device includes a cell region in which a memory cell array is disposed, and a peripheral circuit region at least partially vertically overlapping the cell region. The peripheral circuit region includes a first sub-peripheral circuit region, and a second sub-peripheral circuit region at least partially vertically overlapping the first sub-peripheral circuit region. A thickness of a first lowermost inter-layer dielectric (ILD) region of the first sub-peripheral circuit region is different from a thickness of a second lowermost ILD region of the second sub-peripheral circuit region.