Stacked Image Sensor A/D Circuit Layout for Higher Pixel Opening
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Solution Overview
Problem
Existing image sensors with multiple semiconductor chips require larger chip areas due to the disposition of multiple elements, leading to increased size and potential reduction in opening ratio of pixels.
Innovation Solution
The image sensor is designed with a photoelectric conversion unit and an A/D conversion unit that includes a comparison unit and capacitors laminated across multiple substrates, allowing capacitors to be disposed without increasing chip area, and by positioning capacitors with varying capacitance values close to or far from the comparison unit to minimize parasitic capacitance effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple semiconductor chips are disposed in the image sensor, then the A/D conversion function is achieved, but the chip area increases
Solution Approach 1:
The patent applies three-dimensional stacking of semiconductor chips to resolve the contradiction. Multiple chips including the photoelectric conversion chip and A/D conversion chip are laminated in the vertical direction, transforming the two-dimensional layout problem into a three-dimensional structure. This allows the A/D conversion function to be achieved without increasing the horizontal chip area, as elements are arranged in multiple layers rather than spreading out in a single plane.
Solution Approach 2:
The patent implements a nested structure where smaller functional units are integrated within larger chip structures. The A/D conversion unit is embedded within the overall sensor chip assembly, with capacitors and comparison units nested within the chip layers. This nesting approach allows multiple functions to coexist in a compact configuration, achieving A/D conversion capability while maintaining small chip area.
2Reliability
If multiple elements are disposed on the chip, then the A/D conversion unit is complete, but the pixel opening ratio decreases
Solution Approach 1:
By moving A/D conversion elements to separate chips in the vertical stacking direction, the patent frees up horizontal space on the photoelectric conversion chip. This dimensional transition allows larger pixel opening ratios to be maintained, as the comparison units and capacitors no longer compete for the same two-dimensional space with the photodiodes.
Solution Approach 2:
The patent extracts the A/D conversion elements (comparison units and capacitors) from the photoelectric conversion chip and places them on separate chips in the stack. This extraction removes the space-consuming A/D components from the pixel array area, thereby preserving the pixel opening ratio while still achieving complete A/D conversion functionality in the multi-chip system.
3Device complexity
If capacitors are placed close to the comparison unit, then the circuit layout is compact, but parasitic capacitance increases
Solution Approach 1:
The patent segments the A/D conversion function into separate chips: the comparison unit remains on the first chip while capacitors are placed on second and third chips. This segmentation physically separates the capacitors from the comparison unit, reducing parasitic capacitance effects. The functional separation allows for more accurate measurements while still maintaining a relatively compact overall structure through the stacked configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances A/D conversion resolution and accuracy by preventing chip area expansion and reducing conversion errors due to parasitic capacitance, while maintaining pixel opening ratio.
Implementation Method 1
a photoelectric conversion unit that photoelectrically converts incident light and generates a charge
Data Source
AI summary
An image sensor includes: a photoelectric conversion unit that photoelectrically converts incident light and generates a charge; and an A/D conversion unit that converts the analog signal generated due to charge generated by the photoelectric conversion unit into a digital signal, wherein: the A/D conversion unit includes a comparison unit that compares the analog signal with a reference signal and a first circuit layer including a first capacitor for generating the reference signal and a second circuit layer laminated to the first circuit layer and including with a second capacitor for generating the reference signal.