Stacked Image Sensor ADC Layout for Reduced Pixel Time Lag
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Solution Overview
Problem
In layered imaging devices, the size reduction of AD converter circuits is hindered by their large transistor count, leading to increased time lags when handling multiple pixels, causing image distortion or prolonged image capture times, especially when imaging moving objects.
Innovation Solution
The solution involves stacking substrates with pixels and a comparing unit on the upper substrate and a storage unit on the lower substrate, utilizing transistors with different power supply voltages and configurations, such as NMOS and PMOS, to optimize circuit size and performance, allowing for parallel AD conversion and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If one AD converter circuit is shared by more than one pixel, then the device size is reduced, but the time lag among pixels increases causing image distortion
Solution Approach 1:
The patent segments the AD converter functionality across multiple substrates in a stacked configuration. Each substrate contains pixels with their own comparing units, while storage units are separated on different substrates. This segmentation allows parallel processing of multiple pixels simultaneously, reducing time lag while maintaining compact form factor through vertical stacking.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture. By stacking multiple substrates vertically, the patent achieves higher integration density without increasing the footprint area. This dimensional change enables multiple AD converter circuits to operate in parallel while maintaining small device size, thereby resolving the contradiction between size reduction and time lag reduction.
2Area of moving object
If pixels are made smaller, then the imaging device size is reduced, but the AD converter circuits become harder to scale down
Solution Approach 1:
The patent employs three-dimensional stacking to separate pixel circuits on one substrate from AD converter circuits on another substrate. This vertical separation allows independent optimization of pixel size without being constrained by the minimum feature size required for AD converter circuits. The stacked architecture enables small pixels to coexist with larger AD converter circuits in the vertical dimension, resolving the scaling contradiction.
Solution Approach 2:
The patent divides the imaging device into functionally separate modules on different substrates: pixel arrays on the upper substrate and AD converter circuits on the lower substrate. This segmentation allows each module to be independently scaled and optimized. Pixels can be miniaturized on one substrate while AD converters maintain adequate size on another substrate, eliminating the mutual constraint in planar integration.
3Loss of time
If more AD converter circuits are provided for parallel processing, then time lag is reduced, but the device size increases
Solution Approach 1:
The patent utilizes vertical stacking to arrange multiple AD converter circuits on different substrates in the third dimension. This three-dimensional configuration enables parallel processing of multiple pixels simultaneously, reducing time lag, while the overall device footprint remains compact because the circuits are stacked vertically rather than spread out horizontally. The stacking architecture decouples processing speed from device area.
Data Source
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AI summary
The present technology relates to an imaging device that can reduce the size thereof, and to an electronic apparatus. An upper substrate and a lower substrate are stacked. A pixel and a comparing unit that compares the voltage of a signal from the pixel with the ramp voltage are provided on the upper substrate, the ramp voltage varying with time. A storage unit that stores a code value obtained at a time when a comparison result from the comparing unit is inverted is provided on the lower substrate. The comparing unit is formed with a transistor that receives the voltage of the signal from the pixel at the gate, receives the ramp voltage at the source, and outputs a drain voltage. Accordingly, the imaging device can be made smaller in size. The present technology can be applied to image sensors.