Floorplan-Optimized Stacked Image Sensor ADC Placement
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Solution Overview
Problem
Conventional stacked CMOS image sensors face limitations in maximizing the footprint of non-ADC circuit elements on the circuit layer, leading to performance inhibition and increased costs due to suboptimal ADC placement, which results in wasted space and potential need for additional circuit layers.
Innovation Solution
A floorplan-optimized stacked image sensor design that partitions pixel sub-arrays into groups and strategically positions ADCs to maximize contiguous and uninterrupted global-based space on the circuit layer, allowing for increased area utilization by other circuit elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ADCs are placed in a conventional stacked image sensor configuration, then each pixel sub-array can be connected to a dedicated ADC, but the footprint of non-ADC circuit elements on the circuit layer is reduced
Solution Approach 1:
The pixel array is divided into multiple pixel sub-arrays (PSAs), and each PSA is assigned to a dedicated ADC. This segmentation allows ADCs to be distributed across the circuit layer in an optimized pattern rather than concentrated in one area, enabling better space utilization for non-ADC circuit elements while maintaining dedicated conversion paths for each PSA.
Solution Approach 2:
The circuit layer is designed with non-uniform ADC placement where ADCs are strategically positioned to serve specific PSAs. This creates local regions with different functional densities - some areas have ADCs while others are dedicated to non-ADC circuit elements like memory and ISPs, optimizing the local quality of each region for its specific function.
2Adaptability or versatility
If more ADCs are added to the circuit layer to serve additional PSAs, then pixel-level or column-level conversion capability is improved, but the space for non-ADC circuit elements is further reduced
Solution Approach 1:
The patent transitions from a single-layer planar arrangement to a stacked three-dimensional architecture. By placing the sensor layer above the circuit layer and using vertical interconnections, the system achieves pixel-level or column-level conversion capability without proportionally increasing the footprint on the circuit layer, as ADCs are vertically integrated with their corresponding PSAs.
Solution Approach 2:
The circuit layer is designed to accommodate multiple functions within the same physical space. Non-ADC circuit elements such as memory, image signal processors, and ADCs share the circuit layer through optimized spatial arrangement, allowing the layer to serve multiple purposes simultaneously - conversion, processing, and storage - without requiring separate dedicated layers for each function.
3Manufacturing precision
If the circuit layer is densely packed with ADCs to maximize conversion capability, then A/D conversion performance is improved, but the overall sensor efficiency is reduced due to wasted space
Solution Approach 1:
The floorplan optimization is performed in advance during the design phase, determining the optimal positions for ADCs and non-ADC circuit elements before manufacturing. This preliminary arrangement ensures that the circuit layer is efficiently utilized with no wasted space, maximizing sensor efficiency while maintaining the precision required for high-quality A/D conversion.
Solution Approach 2:
The patent optimizes the spatial distribution parameters of ADCs on the circuit layer by changing their positions and densities. Rather than uniform distribution, ADCs are placed with varying density in different regions based on the requirements of corresponding PSAs, optimizing both conversion precision and overall space utilization for maximum sensor efficiency.
Data Source
AI summary
A floorplan-optimized stacked image sensor and a method for designing the sensor are disclosed. A sensor layer includes multiple PSAs partitioned into PSA groups. A circuit layer includes multiple analog-to-digital converters each communicatively coupled to a different PSA. Each analog-to-digital converter (ADC) is semi-aligned to the PSA group associated with the PSA to which it is communicatively coupled. The floorplan of ADCs maximizes contiguous global-based space on the circuit layer uninterrupted by an ADC. The resulting circuit layer floorplan has one or more global-based spaces interleaved with one or more local-based spaces containing ADCs.