Stacked Image Sensor Bond Structure With Fewer Conductive Layers

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Solution Overview

Problem

Existing stacked CMOS image sensors face increased resistivity, fabrication costs, and reduced device density due to multiple conductive bonding layers in the bond structures, which also increase design complexity and reduce the ability to scale device features.

Innovation Solution

The stacked CMOS image sensor design incorporates bond structures with one or less conductive bonding layer, utilizing a pixel device chip between the imaging and logic chips, and through-substrate vias to reduce conductive structures and resistivity, thereby decreasing fabrication costs and increasing device density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple conductive bonding layers are used in bond structures, then electrical connections are maintained, but resistivity increases and device density decreases

Engineering Contradiction:
Improveelectrical connectionsVSAvoiddevice density
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent removes unnecessary conductive bonding layers from the bond structure, extracting only the essential single conductive bonding layer that maintains electrical connections while reducing resistivity and increasing device density

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the parameter of conductive bonding layer count from multiple layers to one layer, fundamentally altering the bond structure to achieve lower resistivity and improved device density while maintaining electrical functionality

Inventive Principle:
Principle #35Parameter changes

2Reliability

If multiple conductive bonding layers are used in bond structures, then electrical connections are maintained, but fabrication costs increase

Engineering Contradiction:
Improveelectrical connectionsVSAvoidfabrication costs
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent extracts and removes redundant conductive bonding layers, reducing the total number of layers from multiple to one, which directly decreases fabrication complexity and cost while preserving essential electrical connections

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If multiple conductive bonding layers are used in bond structures, then electrical connections are maintained, but RC delay increases

Engineering Contradiction:
Improveelectrical connectionsVSAvoidRC delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent removes excess conductive bonding layers that contribute to RC delay, retaining only the single essential layer needed for electrical connections, thereby reducing the time constant and improving signal transmission speed

Inventive Principle:
Principle #2Taking out (Extraction)

4Reliability

If multiple conductive bonding layers are used in bond structures, then electrical connections are maintained, but design complexity increases

Engineering Contradiction:
Improveelectrical connectionsVSAvoiddesign complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates redundant conductive bonding layers from the design, simplifying the bond structure to a single layer configuration that reduces design complexity while maintaining all necessary electrical connection functions

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20250318311A1Bonding structures for stacked image sensor
Publication Date: 2025.10.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250318311A1 patent drawing
  • US20250318311A1 patent drawing
  • US20250318311A1 patent drawing

AI summary

Various embodiments of the present disclosure are directed towards an image sensor including first chip and a second chip. The first chip includes a first substrate, a plurality of photodetectors disposed in the first substrate, a first interconnect structure disposed on a front side of the first substrate, and a first bond structure disposed on the first interconnect structure. The second chip underlies the first chip. The second chip includes a second substrate, a plurality of semiconductor devices disposed on the second substrate, a second interconnect structure disposed on a front side of the second substrate, and a second bond structure disposed on the second interconnect structure. A first bonding interface is disposed between the second bond structure and the first bond structure. The second interconnect structure is electrically coupled to the first interconnect structure by way of the first and second bond structures. At least one of the first bond structure and the second bond structure comprises one or less conductive bonding layer.