Stacked Image Sensor Wiring Layout for Stronger Chip Bonding
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Solution Overview
Problem
The existing solid-state image sensors face issues with low bonding strength between semiconductor substrates, leading to void formation and potential separation during the thinning process, particularly when copper electrodes are used as a shielding layer, resulting in compromised image quality.
Innovation Solution
The proposed solution involves bonding semiconductor substrates with overlapping multilayer wiring layers, where the first and second semiconductor substrates have insulating layers with specific wiring configurations that enhance bonding strength and prevent void formation, using copper conductors with asymmetrical surface occupancy ratios to improve bonding efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If copper electrodes are used as shielding layer with high surface occupancy ratio, then light emission from logic circuit is effectively shielded, but bonding strength between semiconductor substrates decreases and void formation occurs
Solution Approach 1:
The patent applies local quality by creating different surface occupancy ratios for copper electrodes in different regions: the first copper electrode (signal line) has a first surface occupancy ratio while the second copper electrode (shielding layer) has a second surface occupancy ratio that is different from the first. This allows the shielding layer to effectively block light emission while maintaining adequate bonding strength by optimizing the copper distribution locally rather than uniformly across the entire substrate surface.
2Object-affected harmful factors
If copper electrodes are used as shielding layer, then light emission is shielded, but void formation occurs during bonding process
Solution Approach 1:
The patent implements local quality by varying the surface occupancy ratio of copper electrodes between the first copper electrode (signal line) and the second copper electrode (shielding layer). This localized differentiation allows the shielding function to be maintained while reducing void formation during bonding, as the optimized copper distribution prevents excessive copper accumulation that would cause bonding defects.
3Strength
If asymmetric surface occupancy ratios are used for copper electrodes, then bonding strength is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by assigning different surface occupancy ratios to different copper electrodes based on their functional requirements. The first copper electrode (signal line) and second copper electrode (shielding layer) have different occupancy ratios optimized for their respective functions, allowing improved bonding strength while maintaining manufacturing feasibility through function-based differentiation rather than uniform design.
Solution Approach 2:
The patent implements multi-functionality by designing the copper electrode system to simultaneously serve multiple functions: signal transmission (first copper electrode), light shielding (second copper electrode), and bonding strength optimization (asymmetric occupancy ratios). This universal approach allows a single electrode structure to fulfill multiple roles, reducing the need for additional separate components and simplifying the overall manufacturing process despite the asymmetric configuration.
Data Source
AI summary
An imaging device comprises a first chip that includes a first semiconductor substrate including a photoelectric conversion region. The first chip includes a first insulating layer including a first multilayer wiring electrically connected to the photoelectric conversion region. The first multilayer wiring includes a first vertical signal line (VSL1) to output a first pixel signal, and a first wiring. The imaging device includes a second chip including a second semiconductor substrate including a logic circuit. The second chip includes a second insulating layer including a second multilayer wiring electrically connected to the logic circuit. The second multilayer wiring includes a second wiring. The first chip and the second chip are bonded to one another, and, in a plan view, the first wiring and the second wiring overlap with at least a portion of the first vertical signal line (VSL1).