Stacked Back-Illuminated Image Sensor Without Cover Glass
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Solution Overview
Problem
Existing back-illuminated solid-state image sensors face challenges in maintaining strength and rigidity due to thin thickness, leading to stress concentration and difficulties in controlling wafer and chip size package processes, while cover glass bonding complicates device thinning and deteriorates imaging characteristics.
Innovation Solution
A stacked-type solid-state image sensor design with a first semiconductor element including a pixel and a second semiconductor element with a logic circuit, connected via a through-silicon via (TSV) for external output, and a wafer support system material bonded on the lens, allowing for wafer process control and device height reduction without cover glass.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the back-illuminated solid-state image sensor is made thin to reduce device height, then device height is reduced, but strength and rigidity deteriorate leading to stress concentration
Solution Approach 1:
The patent employs a stacked-type structure combining a sensor chip with a logic chip, creating a composite assembly that provides both thinness for reduced device height and sufficient strength through the combined structure. The sensor chip and logic chip are bonded together to form a mechanically robust unit that overcomes the weakness of individual thin chips.
Solution Approach 2:
The patent transitions from a single-layer thin structure to a multi-layer stacked structure. By stacking the sensor chip with a logic chip in the vertical dimension, the design achieves reduced footprint while maintaining structural integrity through the distributed mass and bonding interface between layers.
2Strength
If cover glass is bonded to hold rigidity of CSP, then strength is improved, but device thinning is difficult and imaging characteristics deteriorate due to flare
Solution Approach 1:
The patent removes the cover glass component from the traditional CSP structure. Instead of bonding cover glass to achieve rigidity, the design uses the stacked sensor chip and logic chip configuration itself to provide the necessary mechanical strength, thereby eliminating the cover glass and enabling thinner device profiles without flare issues.
3Length of stationary object
If both sensor chip and logic chip are made thin to reduce device height, then device height is reduced, but stress concentration increases due to weak strength
Solution Approach 1:
The patent creates a composite structure where the sensor chip and logic chip are bonded together. This composite assembly distributes mechanical stresses across both chips and their bonding interface, preventing stress concentration that would occur in a single thin chip while maintaining reduced overall device height.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables effective control of wafer and chip size package processes, reduces device height, and maintains imaging quality by eliminating the need for cover glass, thus addressing strength and imaging issues in existing technologies.
Implementation Method 1
a through electrode electrically connecting the first semiconductor element and the second semiconductor element
Implementation Method 2
a pixel including a photoelectric conversion element
Data Source
AI summary
The present disclosure relates to a solid-state image sensor, a manufacturing method, and an electronic device that enable control of a wafer process and a chip size package (CSP) process even with no cover glass. A CIS wafer and a logic wafer including a logic circuit or a memory circuit are stacked and bonded. The CIS wafer and the logic wafer are electrically connected via a through electrode. After formation of a lens on a light receiving surface of the CIS wafer, a wafer support system material is bonded on the lens. An external electrode is formed as an external output, using a TSV formed from a back surface side of the logic wafer that has been made into a thin film. The wafer support system material is then separated from the light receiving surface. The present disclosure can be applied to, for example, a stacked-type back-illuminated solid-state image sensor.