Stacked Image Sensor Diagonal Routing Miniaturization
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Solution Overview
Problem
Current image sensors with stacked semiconductor dies face challenges in miniaturization due to design process margins, limiting their integration and compactness in mobile devices like smartphones and tablets, which increases manufacturing costs and affects performance.
Innovation Solution
The implementation of a stacked image sensor design featuring a first semiconductor die with a pixel array and elongated column interlayer-connection structures, along with diagonal routing wires connecting columns and rows independently, and a second semiconductor die with corresponding interlayer-connection structures and control circuitry, allowing for a slide routing structure that maximizes design margin and minimizes size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional stacked die design is used, then manufacturing cost is reduced, but miniaturization is limited due to design process margins
Solution Approach 1:
The patent transitions from conventional planar routing to a three-dimensional stacked die architecture with vertical interlayer connections. Column routing wires extend through multiple die layers, and interlayer-connection structures are positioned at different vertical levels, enabling miniaturization by utilizing the third dimension (vertical stacking) rather than expanding horizontally.
Solution Approach 2:
The image sensor is divided into multiple semiconductor dies stacked vertically. The first semiconductor die contains the pixel array, while the second semiconductor die contains control circuitry and additional interlayer-connection structures. This segmentation allows independent optimization of each die and enables compact integration through vertical stacking.
2Volume of moving object
If miniaturization is pursued, then device compactness is improved, but design process margins are reduced
Solution Approach 1:
By moving routing paths to the vertical dimension through stacked dies, the patent reduces lateral routing congestion and increases design process margins in the planar dimensions. The interlayer-connection structures provide dedicated vertical pathways that do not compete for space with pixel arrays or control circuitry layouts.
Solution Approach 2:
The patent implements nested interlayer-connection structures where second column interlayer-connection structures are positioned to align with first column interlayer-connection structures across die boundaries. This nesting approach creates efficient vertical routing pathways that maximize space utilization and maintain design margins.
3Adaptability or versatility
If stacked die architecture is implemented, then integration is improved, but routing complexity increases
Solution Approach 1:
The patent resolves routing complexity by transitioning two-dimensional lateral routing into three-dimensional vertical routing. Column routing wires extend vertically through die layers, and interlayer-connection structures provide organized connection points at different vertical levels, simplifying the routing topology despite the stacked architecture.
Solution Approach 2:
The interlayer-connection structures serve multiple functions: they provide electrical connections between stacked dies, establish vertical routing pathways, and enable alignment references for subsequent bonding processes. This multi-functionality reduces the need for separate dedicated structures, simplifying the overall design.
Data Source
AI summary
A stacked image sensor includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a pixel array of rows and columns of pixels, a first column interlayer-connection unit extending in the row direction and disposed adjacent the top or bottom of the pixel array and column routing wires extending in a diagonal direction and connecting the pixel columns and the first column interlayer-connection unit. The second semiconductor die is stacked with the first semiconductor die. The second semiconductor die includes a second column interlayer-connection unit extending in the row direction and disposed at a location corresponding to the first column interlayer-connection unit and connected to the first column interlayer-connection unit, and a column control circuit connected to the second column interlayer-connection unit.