Stacked Image Sensor Structure for Compact High-Function Integration
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Solution Overview
Problem
Current semiconductor devices face limitations in reducing chip size while maintaining high-performance capabilities, particularly in image sensors, due to the need for compact yet high-resolution imaging and complex circuit integration.
Innovation Solution
The semiconductor device employs a stacked structure with multiple substrates, each performing distinct functions, connected via interconnection vias and layers, allowing for the separation of circuit modules across different substrates to achieve compact size and enhanced functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple circuit modules are integrated on a single substrate, then device functionality is enhanced, but chip size increases
Solution Approach 1:
The patent divides the semiconductor device into multiple separate substrates (first substrate with pixel array, second substrate with circuit modules, third substrate with processing circuits). Each substrate is optimized for its specific function, and they are stacked vertically with interconnection structures (via holes, conductive plugs, bonding pads) to establish electrical connections. This segmentation allows high-functionality integration while maintaining compact chip size through three-dimensional stacking.
Solution Approach 2:
The patent transitions from planar two-dimensional integration to three-dimensional vertical integration by stacking multiple substrates in the thickness direction. The first substrate is positioned at a first level, the second substrate at a second level, and the third substrate at a third level, with interconnection structures extending vertically between levels. This dimensional change enables multiple circuit modules to be integrated without increasing chip area, thereby resolving the contradiction between functionality and chip size.
2Area of stationary object
If circuit modules are separated across multiple substrates, then chip size is reduced, but interconnection complexity increases
Solution Approach 1:
The interconnection system is segmented into distinct components: via holes formed through substrates, conductive plugs filling the via holes, and bonding pads on substrate surfaces. Each component has a specific function and is optimized independently. The via holes provide vertical pathways, the conductive plugs establish electrical continuity, and the bonding pads provide connection interfaces. This segmentation of the interconnection system manages complexity by breaking down the overall connection task into manageable, standardized elements.
Solution Approach 2:
The patent introduces intermediary structures to facilitate connections between substrates. Bonding pads act as intermediaries between the interconnection vias and the circuit modules on each substrate. The conductive plugs serve as intermediaries that bridge the gap between adjacent substrates through the via holes. These intermediary elements simplify the overall interconnection process by providing standardized connection points and reducing the complexity of direct substrate-to-substrate bonding.
3Manufacturing precision
If substrate thickness is increased, then manufacturing precision is improved, but device volume increases
Solution Approach 1:
The patent applies partial thinning to the substrates rather than uniform thinning across the entire device. Specific regions of the substrates are thinned to appropriate thicknesses for their functional requirements, while other regions maintain sufficient thickness for structural integrity and manufacturing precision. This partial action approach allows optimization of substrate thickness locally, improving manufacturing precision where needed while minimizing overall device volume by avoiding excessive thickness in non-critical areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of smaller chip sizes with improved imaging resolution and functionality by separating circuit components across stacked substrates, facilitating efficient signal processing and connection, thereby addressing the limitations of traditional semiconductor designs.
Implementation Method 1
the first interconnect layer and the second interconnect layer are bonded to each other
Data Source
AI summary
A semiconductor device includes a first stacked structure including a first substrate having unit pixels, and a first interconnect layer having first conductive lines connected to the unit pixels; a second stacked structure including a second substrate having first circuit elements configured to operate the unit pixels and a second interconnect layer having second conductive lines connected to the first circuit elements and an electrode pad, and a first interconnection via structure penetrating the second substrate; a third stacked structure including a third substrate having second circuit elements configured to process signals received from the second stacked structure, and a third interconnect layer having third conductive lines connected to the second circuit elements; and a pad open region disposed outside of a pixel region including the unit pixels and exposing a top surface of the electrode pad to outside.