Stacked Image Sensor ICs With Inter-Die Bonds
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Solution Overview
Problem
Image sensor arrays face challenges with high data volume from high-resolution images, defective pixels, and limited integration of memory devices like OTP and DRAM, which affect data processing efficiency and area usage.
Innovation Solution
A three-integrated-circuit sandwich architecture where a pixel array IC is coupled with a logic IC and a DRAM IC through inter-die bonds, allowing for efficient data transfer and buffering of image data in DRAM, while also integrating OTP memory on one IC to manage operations, reducing complexity and area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If OTP memory devices are integrated on the pixel array IC, then nonvolatile storage for defective pixel information is achieved, but fabrication process compatibility is lost
Solution Approach 1:
The system is divided into separate functional ICs: a pixel array IC for light sensing, a logic IC for processing and OTP memory integration, and a DRAM IC for buffering. This segmentation allows each IC to be optimized for its specific function and fabricated using appropriate processes, resolving the contradiction between OTP memory integration and fabrication compatibility.
2Area of stationary object
If DRAM memory is used instead of OTP memory, then area and memory capacity are improved, but nonvolatile storage capability is lost
Solution Approach 1:
The system merges DRAM technology with OTP functionality by integrating OTP memory on the logic IC alongside DRAM buffers. This allows the system to achieve both the area efficiency of DRAM and the nonvolatile storage capability of OTP, resolving the contradiction between area and nonvolatile storage.
3Ease of manufacture
If high on-chip voltages are used for OTP programming, then programming capability is achieved, but area per transistor increases
Solution Approach 1:
The patent moves from a single-IC architecture to a multi-IC stacked architecture. By placing OTP memory on a separate logic IC and using through-silicon vias for inter-IC communication, the system achieves programming capability without the area penalty of high-voltage circuitry on the pixel array IC, effectively resolving the area-transistor density contradiction.
4Productivity
If pixel arrays are formed using standard IC fabrication, then manufacturing scalability is achieved, but floating-gate multilayer-polysilicon OTP memory integration is lost
Solution Approach 1:
The logic IC serves multiple functions: it contains OTP memory for storing defective pixel information, includes processing logic for image data, and provides interfaces to both the pixel array IC and DRAM IC. This multi-functionality allows standard IC fabrication to be used while still achieving OTP memory integration through the separate logic IC.
Data Source
AI summary
A multiple IC, buffered, image sensor has a first IC with pixels, selection transistors, and interconnect coupling selected pixels with first inter-die bond pads that convey image data to a second IC having logic and ADCs. The ADCs having inputs coupled to selected pixels and outputting through-silicon vias and inter-die bond pads to a third IC coupled to buffer raw image data in DRAM. A method includes capturing images with array pixel IC divided into sub-arrays each coupled to a separate, associated, ADC through inter-die bonds, scanning the sub-arrays and converting the image data to digital image data; and transferring the digital image data over inter-die bonds into buffers in DRAM.