Stacked Image Sensor Interconnect Layout for Larger Pixel Arrays
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Solution Overview
Problem
Current imaging sensors face challenges in optimizing pixel array size on a substrate while maintaining high-quality signal processing, particularly due to size constraints and the need for smaller contact pads, which limits the integration of supporting circuitry and increases manufacturing costs.
Innovation Solution
The solution involves a stacking scheme where the pixel array is optimized on a first substrate, and supporting circuitry is located on subsequent substrates, using advancements in back-side illumination and three-dimensional stacking technology to maximize pixel array size without sacrificing image quality, with interconnects and vias connecting the substrates for electrical communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pixel array area is increased on a single substrate, then the resolution and data capacity are improved, but the chip size becomes larger and contact pads must be made smaller
Solution Approach 1:
The patent transitions from a two-dimensional single-substrate layout to a three-dimensional stacked architecture. Multiple substrates are stacked vertically, with pixel arrays on some substrates and supporting circuitry on others. This vertical stacking enables the pixel array area to be increased across multiple layers while maintaining a compact footprint on each individual substrate, effectively resolving the contradiction between large pixel array area and small chip size.
Solution Approach 2:
The imaging sensor is divided into multiple independent substrates, each with specific functions. Some substrates are dedicated to pixel arrays while others contain supporting circuitry such as A/D converters and amplifiers. This segmentation allows the pixel array area to be maximized on dedicated substrates without being constrained by the need to accommodate all circuitry on a single large chip.
2Area of stationary object
If contact pads are made smaller to fit more circuits, then the chip area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
By stacking substrates vertically, the patent moves contact pads and interconnects into the third dimension. Through-silicon vias (TSVs) and vertical interconnects replace traditional planar contact pads, allowing electrical connections between stacked substrates without requiring extremely small lateral features. This vertical interconnection approach reduces the manufacturing precision burden while achieving compact chip area.
3Reliability
If supporting circuitry is integrated on the same substrate as the pixel array, then signal processing quality is maintained, but the pixel array area is reduced
Solution Approach 1:
The patent segments the imaging sensor into functionally specialized substrates. Pixel arrays are placed on dedicated substrates where they can occupy maximum area without competing for space with supporting circuitry. Other substrates are dedicated to signal processing functions such as amplification and A/D conversion. This functional segmentation maintains signal processing quality while maximizing pixel array area through the stacked architecture.
Solution Approach 2:
The patent introduces vertical interconnects and intermediary circuit layers between the pixel array substrates and processing circuit substrates. These intermediaries efficiently transmit signals between layers while maintaining signal integrity, allowing supporting circuitry to be physically separated on different substrates without degrading signal processing quality.
Data Source
AI summary
Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed.