Stacked Image Sensor Knee Point Calibration
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Solution Overview
Problem
CMOS image sensors face limitations in dynamic range and are prone to fixed pattern noise due to variations in pixel responsitivity, leading to image degradation, especially when capturing scenes with high contrasts.
Innovation Solution
The design incorporates a stacked chip configuration with rolling shutter and global shutter readout modes, along with a row decoder and programmable function logic circuit to reduce fixed pattern noise and enhance dynamic range, utilizing a self-knee point calibration method to adjust transfer transistor gate voltage levels dynamically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If miniaturization and integration of CMOS image sensors are pursued to meet higher resolution demands, then resolution is improved, but pixel photosensitivity and dynamic range are reduced
Solution Approach 1:
The patent transitions from a planar single-chip architecture to a three-dimensional stacked architecture, separating the photodetector array from the readout circuitry onto different chips. This vertical stacking enables higher resolution in the imaging plane while maintaining large pixel photosensitivity areas, as the readout circuits no longer occupy precious in-pixel area.
Solution Approach 2:
The image sensor is divided into functionally separate modules: a first chip containing the photodetector array and a second chip containing the readout circuitry. This segmentation allows each module to be optimized independently - the photodetectors can be made larger for better photosensitivity while the readout circuits are placed elsewhere, resolving the contradiction between resolution and photosensitivity.
2Device complexity
If rolling shutter readout mode is used to simplify circuit design, then device complexity is reduced, but spatial distortion and temporal noise correlation issues arise
Solution Approach 1:
The stacked architecture with separate readout circuitry enables the sensor to support multiple readout modes (rolling shutter and global shutter) through software configuration rather than requiring separate hardware implementations. This multi-functionality allows the system to achieve global shutter's high image quality without the additional circuit complexity, as the same hardware can operate in different modes.
3Reliability
If global shutter mode is implemented to eliminate spatial distortion, then image quality is improved, but additional transistors or storage components are required in each pixel
Solution Approach 1:
By moving the storage and readout functions to a separate second chip in the stacked architecture, the patent eliminates the need for additional in-pixel transistors and storage components. The global shutter functionality is achieved by transferring charge to memory elements on the remote readout chip rather than requiring on-pixel storage, thus maintaining simple pixel structures while enabling distortion-free imaging.
4Reliability
If fixed pattern noise reduction techniques are applied to improve image quality, then image quality is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent extracts the readout circuitry from the photodetector chip and places it on a separate readout chip. This extraction removes the primary source of fixed pattern noise (the readout circuits) from the pixel array, eliminating the need for precise matching between photodetectors and their associated readout circuits. The separation allows independent optimization and reduces sensitivity to manufacturing variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces fixed pattern noise and increases signal dynamic range, allowing for improved imaging of both bright and dark areas in a scene, enhancing the overall image quality by minimizing artifacts caused by transfer transistor threshold voltage variations.
Implementation Method 1
The bottom chip includes an array of light sensitive regions and structures to capture an image... Each pixel cell has one or more photodiodes... accumulating an image charge in response to light incident upon the photodiode
Data Source
AI summary
An image sensor has a stacked pixel arrangement including both rolling and global shutter readout circuits wherein each pixel includes an adjustable transfer transistor gate voltage level for modifying electric charge within a photodiode during exposure depending on incident light intensity. The sensor also has a row decoder circuit providing readout signals to each row of the imaging cells during both a readout interval and during a calibration interval for each row. The row decoder may employ one of several of its features to provide a self-knee point calibration following an image signal readout in order to minimize photo conversion variations that lead to fixed pattern noise and to enhance dynamic range.


