Stacked Solid-State Image Sensor for Compact Medical Imaging

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Solution Overview

Problem

Conventional solid-state image sensors face challenges in achieving a small form factor due to dead space surrounding the image sensing area, which increases the size of medical devices like endoscopes, affecting image quality and patient comfort.

Innovation Solution

A stacked MOS sensor structure is implemented, where the first semiconductor chip contains only the image sensing area, and the second chip holds peripheral circuits, allowing for a smaller footprint and reduced dead space, with global wiring and input protection circuits arranged to minimize electro-static discharge and align the image sensing area with the optical center.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If peripheral circuits are integrated around the image sensing area on the same chip, then the sensor can be manufactured using standard MOS wafer process, but the dead space increases and the form factor becomes larger

Engineering Contradiction:
ImprovemanufacturabilityVSAvoidform factor
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The sensor is divided into two separate chips: a first chip containing only the image sensing area and a second chip containing all peripheral circuits. This segmentation eliminates the dead space problem by removing peripheral circuits from the first chip, allowing the image sensing area to be maximized while maintaining manufacturability through standard MOS processes for each chip separately.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a planar integration approach to a three-dimensional stacked architecture. By stacking the first chip (image sensing area) on the second chip (peripheral circuits), the design utilizes the vertical dimension to separate functional areas, thereby reducing the horizontal footprint and eliminating dead space while maintaining all necessary circuit functions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If the image sensing area is reduced to decrease dead space, then the form factor decreases, but the sensitivity and image quality deteriorate

Engineering Contradiction:
Improveform factorVSAvoidsensitivity
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

By segmenting the sensor into dedicated image sensing chip and peripheral circuit chip, the image sensing area on the first chip can be maximized without compromise from peripheral circuit requirements. This ensures high sensitivity and image quality while achieving a compact overall form factor through the stacked configuration.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The stacked three-dimensional architecture allows the image sensing area to occupy the entire surface of the first chip without dead space, maximizing the light-receiving area and sensitivity. The peripheral circuits are relocated to the second chip in the vertical dimension, enabling the first chip to achieve 100% active pixel area ratio.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Device complexity

If peripheral circuits are placed on the same chip as the image sensing area, then the device complexity is reduced, but the alignment between optical center and image sensing area becomes misaligned

Engineering Contradiction:
Improvestructural complexityVSAvoidalignment precision
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

Segmenting the sensor into separate imaging chip and circuit chip allows each chip to be optimized independently. The first chip can be precisely aligned with the optical center since it contains only the image sensing area, while the second chip handles all peripheral circuits. This eliminates the misalignment problem inherent in integrated designs.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The stacked chip structure acts as an intermediary solution that separates the optical path requirements from the circuit integration requirements. The first chip interfaces directly with the optical system with perfect alignment, while the second chip provides circuit functions through vertical stacking, eliminating the need for complex lateral routing and alignment adjustments.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration results in a more compact imaging system with improved sensitivity and reduced patient discomfort during medical procedures, while also lowering production costs and device size.

Implementation Method 1

an optoelectronic conversion device including, for example, a pn-junction photo-diode

Methodology Applied
Scientific EffectPhotoelectric effect: Photoelectric Effect

Data Source

PatentUS9634060B2Stacked solid-state image sensor and imaging apparatus including the same
Publication Date: 2017.04.25 SHIZUKUISHI MAKOTO
  • US9634060B2 patent drawing
  • US9634060B2 patent drawing
  • US9634060B2 patent drawing

AI summary

An image sensor includes a first semiconductor chip having a first surface and a second surface, the first semiconductor chip a including an array of unit pixels configured to capture light corresponding to an image and to generate image signals based on the captured light; and a second semiconductor chip having a first surface and a second surface, the second semiconductor chip including first peripheral circuits configured to control the array of pixels and receive the generated image signals, the first peripheral circuits including a vertical scanning circuit, a horizontal scanning circuit, and a signal read-out circuit, the first semiconductor chip being stacked on the second semiconductor chip, the first semiconductor chip not being smaller than the second semiconductor chip.