Stacked Image Sensor Package with Memory Die
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional image sensor packages face challenges in packaging frame memory without deformation, leading to yield decreases due to size and capacity changes, and high-temperature processes associated with wafer bonding.
Innovation Solution
A stacked image sensor package is developed with a pixel array die and logic die stacked using wafer-to-wafer bonding, and a memory die is connected via a redistribution layer and external connectors, allowing for desired capacity and size without generation changes, using a chip-on-wafer method to reduce yield loss and avoid high-temperature processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If wafer-to-wafer bonding method is used to stack pixel array die and logic die, then the size of the entire die/module is reduced, but high-temperature process causes yield decrease and memory chip characteristic deterioration
Solution Approach 1:
The patent divides the bonding process into two separate stages: first stacking the pixel array die and logic die using wafer-to-wafer bonding, then separately packaging the memory die using chip-on-wafer method. This segmentation allows each component to be processed under optimal conditions, avoiding high-temperature exposure for the memory die while maintaining the size reduction benefits of wafer bonding for the image sensor stack.
Solution Approach 2:
The patent introduces an intermediary approach by using chip-on-wafer method as a bridge between the stacked image sensor and the memory die. This intermediary packaging method allows the memory die to be connected without requiring high-temperature wafer bonding, thus protecting memory chip characteristics while achieving integration.
2Adaptability or versatility
If memory is packaged by wafer-to-wafer method, then integration is achieved, but overlap loss increases and yield decreases
Solution Approach 1:
The patent segments the packaging process into distinct stages: wafer-to-wafer bonding for the image sensor components followed by chip-on-wafer method for memory die attachment. This segmentation eliminates the overlap loss issue inherent in wafer-to-wafer memory packaging while maintaining integration capability through the intermediate stacked image sensor structure.
Solution Approach 2:
The patent performs preliminary stacking of the pixel array die and logic die using wafer-to-wafer bonding before memory die packaging. This preliminary action creates a stable base structure, allowing subsequent memory die attachment using the more yield-friendly chip-on-wafer method without requiring memory dies to be bonded in the initial wafer-to-wafer process.
3Loss of time
If frame memory is packaged in the image sensor, then readout time is decreased, but deformation of frame memory occurs and yield decreases due to size or capacity changes
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional stacked architecture, placing the memory die on the rear surface of the stacked image sensor. This vertical arrangement in another dimension allows the frame memory to be integrated without deforming the image sensor structure, as the memory die is attached after the image sensor stack is completed using the chip-on-wafer method.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces yield loss and prevents characteristic deterioration of memory chips, enabling efficient packaging of memory with desired capacity and size without size or capacity changes, and improves light sensitivity and efficiency by minimizing the impact of high-temperature processes.
Implementation Method 1
a pixel array die and a logic die are stacked
Implementation Method 2
a redistribution layer formed on one surface of the stacked image sensor, rerouting an input/output of the stacked image sensor
Implementation Method 3
external connectors connected with the second pad, electrically connecting the memory die and the stacked image sensor with an external device
Data Source
AI summary
Provided are a stacked image sensor package and a packaging method thereof. A stacked image sensor package includes: a stacked image sensor in which a pixel array die and a logic die are stacked; a redistribution layer formed on one surface of the stacked image sensor, rerouting an input/output of the stacked image sensor, and including a first pad and a second pad; a memory die connected with the first pad of the redistribution layer and positioned on the stacked image sensor; and external connectors connected with the second pad, connecting the memory die and the stacked image sensor with an external device, and having the memory die positioned therebetween.