Stacked Image Sensor Parallel Readout for Frame Rate and Power
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Solution Overview
Problem
Existing image sensors face challenges in balancing power saving with maintaining frame rate due to increased data amounts, particularly when performing focus detection and image capture simultaneously.
Innovation Solution
A multilayer image sensor with stacked substrates, where a pixel array on one substrate is paired with signal processing units on another, utilizing shared signal lines for efficient data transfer and analog-to-digital conversion, allowing for parallel and sequential readout operations to reduce data conversion time and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If individual pixels perform both focus detection and image capture simultaneously, then multifunctionality is achieved, but the amount of data increases causing longer readout time and lower frame rate
Solution Approach 1:
The pixel array is divided into multiple pixel blocks, with each block processed by a dedicated signal processing unit. This segmentation allows parallel processing of multiple blocks simultaneously, increasing the overall frame rate despite the increased data volume from multifunctional operation.
Solution Approach 2:
The patent transitions from a planar pixel arrangement to a three-dimensional stacked structure where pixel blocks are vertically aligned with signal processing units. This vertical stacking enables parallel processing paths, allowing simultaneous focus detection and image capture without sequential processing delays that would reduce frame rate.
2Adaptability or versatility
If individual pixels perform both focus detection and image capture simultaneously, then multifunctionality is achieved, but power consumption increases
Solution Approach 1:
Multiple pixel blocks share common signal lines and are processed by dedicated signal processing units that handle both focus detection and image capture data. This merging reduces the total number of independent signal paths and processing circuits, thereby reducing overall power consumption compared to having completely separate processing paths for each function.
Solution Approach 2:
The signal processing units are designed to handle multiple types of data (focus detection and image capture) through a unified processing architecture. This universal processing approach eliminates the need for separate dedicated circuits for each function, reducing power consumption while maintaining multifunctionality.
3Speed
If multiple signal lines connect each signal processing unit to pixel blocks, then data transfer efficiency is improved, but device complexity increases
Solution Approach 1:
The signal processing system is segmented into multiple dedicated units, each handling a specific pixel block. This segmentation localizes the complex multi-line connections to specific regions, making the overall system more manageable and maintainable despite the increased complexity within each local connection set.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables reduced power consumption while maintaining or increasing frame rates by optimizing data processing and transfer within the image sensor.
Implementation Method 1
a pixel array in which a plurality of pixels for performing photoelectric conversion are disposed in matrix
Data Source
AI summary
A pixel array includes a plurality of pixel blocks each formed of a plurality of pixels. A signal processing unit and a corresponding one of the pixel blocks are connected by a plurality of first signal lines. The signal processing unit and a corresponding one of transfer units are connected by a plurality of second signal lines. The signal processing unit includes a conversion circuit that sequentially performs analog-to-digital conversion on first signals input from the plurality of first signal lines during an identical period. The transfer units are disposed in a direction different from a first direction in which the first signal lines are provided, with respect to the circuit array in a second substrate.