3D Stacked Image Sensor Structure for Smaller Pixels and Higher Light Capture
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Solution Overview
Problem
Existing image sensors face challenges with pixel size limitations due to alignment issues in through-silicon via technology, leading to inefficient light capture and processing, and traditional CCD sensors suffer from slow image data transfer and limited light sensitivity due to shared space with control circuits.
Innovation Solution
Implementing monolithic 3D integration through layer transfer technology to stack photodetectors and read-out circuits, allowing for parallel data collection and reduced pixel sizes, and integrating multiple image sensor arrays with distinct focal planes to enhance light sensitivity and dynamic range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If through-silicon via technology is used to integrate photodetectors and read-out circuits, then device integration is achieved, but pixel size is limited due to alignment issues
Solution Approach 1:
The patent transitions from planar 2D integration to 3D vertical stacking by transferring photodetector layers onto read-out circuit substrates. This dimensional change allows integration without relying on through-silicon via alignment, as connections are made through vertical stacking with oxide-to-oxide bonding and via structures that tolerate misalignment better than through-silicon approaches.
Solution Approach 2:
The device is divided into separate functional layers: photodetector layers transferred onto read-out circuit substrates. This segmentation allows independent optimization of each layer and eliminates the need for through-silicon via alignment between tightly integrated components, as each layer can be processed and optimized separately before stacking.
2Area of stationary object
If photodetectors and control circuits share the same space, then device area is reduced, but image data transfer speed decreases and light sensitivity is limited
Solution Approach 1:
The patent separates photodetectors and read-out circuits into different vertical layers rather than placing them side-by-side in the same plane. This 3D stacking approach reduces the planar footprint while enabling direct vertical connections that improve data transfer speed and maintain light sensitivity by dedicating specific layers to specific functions.
3Area of moving object
If pixel size is reduced to increase resolution, then more pixels fit in the sensor area, but light capture efficiency decreases
Solution Approach 1:
By stacking multiple photodetector layers vertically, the patent increases the total light-sensitive volume without increasing the planar pixel footprint. Each layer can be optimized for different wavelength ranges, and the vertical stacking allows more photodetectors to capture light from the same optical footprint, effectively increasing light capture efficiency while maintaining small pixel sizes.
4Reliability
If multiple image sensor arrays with distinct focal planes are integrated, then light sensitivity and dynamic range are enhanced, but device complexity increases
Solution Approach 1:
The patent divides the imaging function into multiple separate photodetector layers, each potentially optimized for different focal planes or wavelength ranges. These segmented layers are transferred onto a common read-out circuit substrate, allowing complex multi-focal-plane functionality to be achieved through modular layering rather than integrating all functions into a single complex structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Achieves improved light capture efficiency, reduced pixel sizes, and high dynamic range imaging by eliminating shifting delays and optimizing sensor layout for enhanced performance.
Implementation Method 1
the second level is bonded to the first level via an oxide-to-oxide bond
Data Source
AI summary
A method for fabricating an integrated device, the method including: forming a first level including a first mono-crystal layer, where forming the first level includes forming a plurality of single crystal transistors, a plurality of pixel control circuits, and a plurality of recessed channel transistors therein; disposing an overlying oxide on top of the first level; providing a second level including a second mono-crystal layer, where the second mono-crystal layer includes a plurality of image sensors; bonding the second level to the first level via an oxide-to-oxide bond such that the second level overlays the oxide; and including disposing a third level underneath the first level, where the third level includes a plurality of third transistors, and where the plurality of third transistors each include a single crystal channel.