3D Stacked Image Sensor Layout for Faster TSV Readout
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Solution Overview
Problem
Conventional CMOS image sensors suffer from high RC delay and slow readout speed due to long conductive paths and TSVs, which result in increased chip size and decreased performance.
Innovation Solution
A high-speed readout image sensor design that includes a first chip with vertically extending TSVs and a second chip with readout circuits positioned laterally between TSVs, reducing overall conductive path lengths and minimizing RC delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional CMOS image sensor design is used with long conductive paths and TSVs, then chip size can be reduced, but RC delay increases and readout speed decreases
Solution Approach 1:
The patent transitions from a planar 2D layout to a 3D stacked architecture where photodetector cells and readout circuits are positioned on different chips vertically aligned. This dimensional change allows conductive paths to extend vertically through TSVs rather than horizontally across the chip, effectively reducing the lateral conductive path length while maintaining functional connectivity.
Solution Approach 2:
The image sensor is divided into multiple independent chips: a first chip containing photodetector cells and a second chip containing readout circuits. This segmentation allows each chip to be optimized independently and enables vertical stacking, which reduces the horizontal conductive path length by eliminating long lateral interconnections.
2Reliability
If conventional CMOS image sensor design with long conductive paths is used, then device complexity can be reduced, but RC delay increases and performance decreases
Solution Approach 1:
By stacking chips vertically and using TSVs for inter-chip communication, the patent reduces lateral signal path lengths, thereby reducing RC delay and improving performance. The vertical 3D architecture replaces long horizontal interconnections with shorter vertical through-silicon vias.
Solution Approach 2:
Through-silicon vias (TSVs) serve as intermediary conductive structures that enable vertical electrical connections between the photodetector chip and readout circuit chip. These TSVs replace long lateral conductive paths with shorter vertical paths, reducing RC delay while maintaining signal integrity.
3Speed
If long conductive paths and TSVs are used in conventional design, then manufacturing can be simplified, but RC delay increases and readout speed decreases
Solution Approach 1:
Dividing the image sensor into separate photodetector and readout circuit chips allows each to be manufactured and optimized independently using standard CMOS processes. The segmented architecture enables vertical stacking with TSVs, reducing lateral conductive path lengths and improving readout speed despite increased manufacturing steps.
Solution Approach 2:
The patent replaces lateral planar interconnections with vertical through-silicon via connections. This substitution of the conductive path geometry reduces the effective path length for signal transmission, thereby reducing RC delay and improving readout speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a fast readout speed with reduced RC delay and increased chip performance by shortening conductive paths, resulting in quicker signal settling times and improved image sensor efficiency.
Implementation Method 1
The image sensors comprise one or more photodetectors (e.g., photodiodes, phototransistors, photoresistors, etc.) configured to absorb incident radiation and output electrical signals corresponding to the incident radiation
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated chip structure. The integrated chip structure includes a first transistor cell and a second transistor cell disposed in a transistor cell array within a first semiconductor substrate. The first transistor cell and the second transistor cell respectively include a plurality of transistors. A first through-substrate via (TSV) and a second TSV are arranged in a TSV array and extend vertically through the first semiconductor substrate. The first transistor cell is electrically coupled to the first TSV and the second transistor cell is electrically coupled to the second TSV. A first readout circuit is disposed within a second semiconductor substrate. The first readout circuit is electrically coupled to the first TSV and to the second TSV.