Stacked Image Sensor Bonding Structure for EMI Shielding
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Solution Overview
Problem
Existing image sensors face challenges in effectively integrating logic and sensor functions, leading to signal interference between stacked chips, which affects performance and efficiency.
Innovation Solution
The proposed image sensor design involves sequentially stacking a logic chip and a sensor chip, with a bonding layer and wiring structure that allows for contact between conductive pads and wiring lines, and the use of shield structures to prevent electromagnetic interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If logic chip and sensor chip are sequentially stacked to integrate functions, then device functionality is improved, but signal interference between chips increases
Solution Approach 1:
A bonding layer is introduced as an intermediary between the logic chip and sensor chip. This bonding layer includes upper and lower bonding layers with dielectric materials that electrically isolate the two chips while maintaining physical contact for mechanical support and signal transmission through controlled connections.
Solution Approach 2:
The bonding layer is segmented into distinct upper and lower bonding layers, each serving specific functions. The upper bonding layer connects to the logic chip while the lower bonding layer connects to the sensor chip, allowing independent optimization of each interface and reducing cross-interference between the chips.
2Reliability
If conductive pads and wiring lines are used to connect chips, then electrical connection is improved, but electromagnetic interference increases
Solution Approach 1:
Dielectric layers are introduced as intermediaries between conductive pads and wiring lines. These dielectric layers electrically isolate adjacent conductive elements while allowing controlled electrical connections through designated via holes, reducing electromagnetic coupling between signal lines.
Solution Approach 2:
The wiring structure transitions from planar two-dimensional layout to three-dimensional stacked architecture. Conductive pads and wiring lines are arranged in multiple vertical layers separated by dielectric materials, allowing signal routing in the vertical dimension to reduce cross-talk and electromagnetic interference in the horizontal plane.
3Reliability
If shield structures are added to prevent interference, then signal quality is improved, but device complexity increases
Solution Approach 1:
The bonding layer serves multiple functions simultaneously: it provides mechanical support for chip bonding, electrical isolation between logic and sensor chips, structural framework for wiring layers, and partial shielding against electromagnetic interference. This multi-functionality reduces the need for separate dedicated shielding structures.
Solution Approach 2:
The shielding function is merged with the bonding layer structure. Conductive elements within the bonding layer are configured to provide both electrical connections and electromagnetic shielding, combining two previously separate functions into a single integrated structure that reduces overall device complexity.
4Reliability
If multiple wiring layers are used to connect chips, then connection reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The bonding layer structure, including dielectric layers and conductive patterns, is prepared in advance before chip bonding. Wiring lines and pads are pre-formed on the bonding layer substrates, allowing subsequent chip attachment to complete the electrical connections without requiring complex post-bonding wiring operations.
Solution Approach 2:
Instead of adding multiple horizontal wiring layers that would require sequential manufacturing steps, the design utilizes vertical stacking of bonding layers with through-silicon vias and vertical conductors. This three-dimensional wiring approach achieves multiple connection functions with fewer discrete manufacturing steps by exploiting the vertical dimension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces signal interference between the sensor and logic chips, enhances fabrication processes, and improves the overall performance and efficiency of the image sensor by minimizing additional wiring layers and facilitating better chip integration.
Implementation Method 1
The upper bonding layer and the lower bonding layer may be in contact with each other
Implementation Method 2
an upper shield structure and a lower shield structure each of which penetrates the upper dielectric layer and the lower dielectric layer, respectively
Data Source
AI summary
An image sensor includes a sensor chip and a logic chip. The sensor chip includes a first substrate, an upper bonding layer, a first wiring layer, and the logic chip includes a second substrate, a lower bonding layer, a second wiring layer. The upper and lower bonding layers contact each other, with the upper bonding layer including an upper dielectric layer, an upper conductive pad, an upper shield structure, and an upper wiring line, and the lower bonding layer including a lower dielectric layer, a lower conductive pad, a lower shield structure, and a lower wiring line. The upper wiring line, upper conductive pad, and upper shield structure being one body, and the lower wiring line, lower conductive pad, and lower shield structure being one body, the upper and lower conductive pads overlap and contact each other, and the upper and lower wiring lines overlap and contact each other.