Stacked Global Shutter Image Sensor for Low-Noise Small Pixels
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Solution Overview
Problem
Existing image sensors face challenges in integrating pixel units, global shutter circuits, and logic circuits efficiently, leading to issues with noise and capacitance, which affect performance and pixel size.
Innovation Solution
A stack structure is implemented with a first layer containing pixel units, a second layer with global shutter circuits, and a third layer with logic circuits, bonded using copper-based bonding structures and through-silicon vias to enhance integration and reduce noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pixel units, global shutter circuits, and logic circuits are integrated in a planar structure, then device functionality is achieved, but noise and capacitance increase affecting performance
Solution Approach 1:
The patent transitions from a planar integration structure to a three-dimensional stacked structure, where pixel units, global shutter circuits, and logic circuits are arranged in separate layers vertically. This dimensional change separates noisy circuits from sensitive pixel units, reducing noise interference while maintaining functional integration.
Solution Approach 2:
The image sensor is divided into multiple functional layers: a first layer containing pixel units, a second layer containing global shutter circuits, and a third layer containing logic circuits. This segmentation isolates noise-generating circuits from sensitive photodetection elements, reducing overall system noise.
2Adaptability or versatility
If more circuits are integrated into the pixel array, then functionality is enhanced, but pixel size increases
Solution Approach 1:
By moving global shutter circuits and logic circuits to separate layers (second and third layers), the patent frees up horizontal space within the pixel array. This allows pixel units to maintain smaller sizes while the enhanced functionality is achieved through vertical stacking of additional circuit layers.
Solution Approach 2:
The patent implements a nested structure where multiple functional circuits are stacked vertically within the footprint of a single pixel unit. The pixel units in the first layer are positioned beneath global shutter circuits in the second layer and logic circuits in the third layer, allowing dense integration without increasing pixel area.
3Strength
If copper-based bonding structures are used to bond layers, then bonding strength is improved, but manufacturing complexity increases
Solution Approach 1:
Copper bonding pads are formed on the bonding surfaces of each layer before the actual bonding process. This preliminary preparation ensures that the copper structures are ready for bonding, achieving strong metallurgical bonds while organizing the manufacturing process into manageable sequential steps.
Solution Approach 2:
Copper serves as an intermediary bonding material between the semiconductor layers. The copper bonding pads on adjacent layers are brought into contact and bonded together, providing strong electrical and mechanical connection while allowing for alignment tolerance and stress management in the stacked structure.
Data Source
AI summary
Provided is an image sensor including a first layer including a first semiconductor substrate including a pixel unit in which a plurality of unit pixels are provided, and a first wiring layer provided on the first semiconductor substrate, a second layer including a second semiconductor substrate on which a plurality of transistors configured to operate a global shutter operation are provided, and a second wiring layer provided on the second semiconductor substrate, and provided on the first layer such that the first wiring layer and the second wiring layer oppose each other in a first direction, a plurality of first bonding structures bonding the first layer to the second layer based on a first bonding metal exposed on a surface of the first wiring layer being in contact with a second bonding metal exposed on a surface of the second wiring layer, a third layer including a third semiconductor substrate on which a logic circuit is provided, and a third wiring layer provided on the third semiconductor substrate, and bonded to the second layer such that the second semiconductor substrate and the third wiring layer oppose each other in the first direction, and a plurality of second bonding structures extending from the second wiring layer, and bonding the second layer to the third layer based on a bonding via penetrating the second semiconductor substrate being in contact with a third bonding metal exposed to a surface of the third wiring layer.