Stacked Image Sensor with Segmented Intermediate Substrate
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Solution Overview
Problem
Current image sensors face challenges in achieving high integration and miniaturization while maintaining performance, particularly in reducing the thickness of the intermediate substrate to enhance sensor characteristics and manufacturing efficiency.
Innovation Solution
The image sensor design involves a stacked structure with a lower device on a lower substrate, an intermediate device on an intermediate substrate, and an upper device on an upper substrate, where the intermediate substrate includes a stack of semiconductor layers and buried insulation patterns, allowing for a reduced thickness of the second semiconductor layer pattern to less than 1 μm, which decreases the overall thickness of the intermediate substrate and improves sensor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the intermediate substrate thickness is reduced to less than 1 μm, then the overall sensor size and compactness are improved, but the manufacturing precision and structural stability become more difficult to maintain
Solution Approach 1:
The intermediate substrate is segmented into multiple functional layers including a first semiconductor layer, a first insulating layer, and a second semiconductor layer pattern, allowing each layer to be optimized independently for both thickness reduction and manufacturing precision
Solution Approach 2:
A first insulating layer is introduced as an intermediary between the first and second semiconductor layers, providing structural support and electrical isolation that enables the second semiconductor layer to be made extremely thin while maintaining manufacturability and stability
2Measurement precision
If the second semiconductor layer pattern thickness is reduced to less than 1 μm, then conversion gain is increased, but noise and manufacturing difficulty increase
Solution Approach 1:
The first insulating layer acts as a mediator that electrically isolates the thin second semiconductor layer from the first semiconductor layer, reducing noise interference while enabling the thin layer design that increases conversion gain
Solution Approach 2:
The second semiconductor layer pattern is selectively positioned and configured in specific regions where high conversion gain is needed, with local optimization of thickness and geometry to maximize performance while controlling noise
3Productivity
If the intermediate substrate is made thinner, then manufacturing efficiency is improved, but device complexity and structural stability worsen
Solution Approach 1:
The intermediate substrate is divided into distinct functional layers that can be manufactured and processed independently, improving manufacturing efficiency through modular fabrication while the clear functional separation reduces overall structural complexity
Solution Approach 2:
Each layer in the intermediate substrate serves multiple functions - the first insulating layer provides both electrical isolation and structural support, while the layered structure enables both thinness for efficiency and complexity management through functional integration
Data Source
AI summary
An image sensor may include a lower device on a lower substrate, an intermediate device on an intermediate substrate on the lower substrate, and an upper device on an upper substrate on the intermediate substrate. The lower device may include a logic transistor. The intermediate device may include at least one transistor. The upper device may include a photodiode and a floating diffusion region. The lower substrate, the intermediate substrate and the upper substrate may be stacked. The intermediate substrate may include a stack of a first semiconductor layer, a silicon oxide layer, and a second semiconductor layer pattern. An insulation pattern fills an opening at least partially defined by one or more inner surfaces of the first semiconductor layer. A buried insulation pattern fills a trench extending through the second semiconductor layer pattern.