Stacked Image Sensor TSV Structure for Fine-Pitch Miniaturization
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Solution Overview
Problem
Current image sensing devices face challenges in miniaturization and integration, requiring finer patterns and narrower pitch lines to meet demands in various applications, but existing technologies struggle to achieve these without compromising performance.
Innovation Solution
The implementation of a scaled through-silicon via (TSV) in image sensors, allowing for a sequential stack of chips with narrower through vias and reduced design rules, enabling more compact and efficient image sensor design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional through-silicon via (TSV) structures are used in image sensors, then manufacturing is easier with standard design rules, but line width and pitch cannot be sufficiently reduced, limiting miniaturization
Solution Approach 1:
The patent applies parameter changes by transitioning from conventional cylindrical TSV structures to inverted tapered TSV structures with specific width profiles. The via width is reduced to 1/4 to 1/10 of the conventional width at the bottom portion, enabling finer pitch lines and miniaturization while maintaining manufacturability through controlled width parameters throughout the via structure
2Quantity of substance
If conventional TSV structures are used, then design rules remain standard, but integration density and miniaturization are compromised
Solution Approach 1:
The patent employs dimensionality change by implementing inverted tapered TSV structures that extend vertically through the silicon substrate with controlled width variations at different depths. This three-dimensional structural optimization allows higher integration density by reducing horizontal footprint while maintaining vertical connectivity, effectively utilizing the Z-dimension to resolve the contradiction between density and complexity
3Length of moving object
If TSV width is reduced for miniaturization, then line width and pitch are improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by implementing non-uniform width distribution within the TSV structure. The via has different width characteristics at different portions: wider at the top for easier alignment and manufacturing, and significantly narrower at the bottom (1/4 to 1/10 width) for miniaturization. This localized quality variation allows achieving fine pitch requirements while maintaining manufacturing precision through appropriate width control at each specific location
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of miniaturized image sensors with improved performance by reducing line width and pitch, facilitating higher integration density and enhanced operational characteristics.
Implementation Method 1
Each of the pixels may include, for example, a photodiode (PD). The photodiode may serve to convert incident light into an electrical signal.
Data Source
AI summary
An image sensor comprises a first and second chips. The first chip includes a first semiconductor substrate, a photoelectric conversion layer in the first semiconductor substrate, a color filter, a micro lens, a first transistor adjacent to the photoelectric conversion layer, a first insulating layer, and a first metal layer in the first insulating layer and connected to the first transistor. The second chip includes a second insulating layer, a second semiconductor substrate, a second transistor on the second semiconductor substrate, a second metal layer in the second insulating layer and connected to a gate structure of the second transistor through a gate contact, a landing metal layer below the second metal layer, and a through via in direct contact with the landing metal layer and vertically passing through the second semiconductor substrate. A width of the through via becomes narrower as the width approaches the third surface.


