Stacked Image Sensor Wafer Architecture for Light Loss Reduction
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Solution Overview
Problem
Current CMOS image sensor manufacturing processes face challenges such as light signal loss due to the distance between the photodiode and lens, lithography process defects, and difficulties in manufacturing capacitors with desired capacitance, especially as device sizes shrink below 90 nm, leading to inefficient light absorption and image quality deterioration.
Innovation Solution
The solution involves manufacturing a photodiode region on one wafer and a transistor and capacitor on a separate wafer, then connecting them using a system in a package (SiP) process, eliminating the need for a microlens and allowing direct light exposure to the photodiode, thereby reducing light loss and improving image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photodiode region, transistor region, and capacitor region are implemented on one wafer during the same fabrication process, then manufacturing process is simplified, but light signal loss increases due to large distance from lens to photodiode caused by BEOL metal lines and capacitor
Solution Approach 1:
The image sensor is divided into two separate wafers: a first wafer containing the photodiode cell and a second wafer containing the transistor and capacitor. This segmentation allows the photodiode to be positioned closer to the lens without the obstruction of BEOL metal lines and capacitors, reducing light signal loss while maintaining the benefits of integrated manufacturing through wafer-level processing.
Solution Approach 2:
The patent transitions from a planar single-wafer architecture to a three-dimensional stacked architecture using SiP technology. By stacking the first wafer (photodiode) on the second wafer (circuit), the patent creates vertical separation that eliminates the horizontal distance problem caused by BEOL layers, allowing direct light exposure to the photodiode while maintaining electrical connectivity through vertical interconnects.
2Productivity
If lithography process is performed on large photodiode region and very small transistor region simultaneously, then manufacturing steps are reduced, but lithography difficulty increases resulting in many defects
Solution Approach 1:
The patent segments the device into two separate wafers processed independently. The first wafer undergoes lithography for the large photodiode region with relaxed precision requirements, while the second wafer undergoes lithography for the small transistor region with appropriate precision control. This eliminates the lithography conflicts that arise from attempting to pattern both large and very small features on the same wafer in the same process step.
3Area of moving object
If device size is reduced using technologies below 90 nm and 65 nm, then integration density increases, but capacitor manufacturing becomes more difficult to achieve desired capacitance
Solution Approach 1:
By separating the capacitor onto a second wafer dedicated to circuit components, the patent allows the capacitor to be manufactured with optimized dimensions and structures independent of the photodiode scaling. This enables the capacitor to achieve desired capacitance values even as the overall device size reduces, since the capacitor can be designed with appropriate area and thickness without being constrained by the photodiode region dimensions.
4Device complexity
If multi-layer metal line and capacitor are manufactured together on one wafer, then manufacturing complexity is reduced, but distance from microlens to photodiode increases causing manufacturing problems
Solution Approach 1:
The patent uses three-dimensional wafer stacking to separate the optical path from the electronic circuitry. The microlens on the first wafer can be positioned directly above the photodiode cell with minimal separation distance, while the multi-layer metal lines and capacitors reside on the second wafer below. This vertical arrangement in the third dimension allows short optical path length while maintaining the necessary electronic components, solving the contradiction between optical performance and circuit integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a high-quality image sensor with reduced light loss, improved manufacturing efficiency, and the ability to integrate a large number of transistors, enabling better image sensor characteristics and performance.
Implementation Method 1
a photodiode region for receiving a light signal and converting it into an electrical signal
Data Source
AI summary
An image sensor and manufacturing process thereof are provided. An image sensor according to an embodiment comprises a first wafer formed with a photodiode cell without a microlens and a second wafer formed with a circuit part including transistor and a capacitor. The first wafer is stacked on the second wafer such that a connecting electrode can be used to electrically connect the photodiode cell of the first wafer to the circuit part of the second wafer.