Stacked Solid-State Imager Wiring for Dense Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing solid-state imaging devices face limitations in reducing size, increasing wiring speed, and enhancing wiring density while maintaining effective light collection characteristics.
Innovation Solution
The development of a solid-state imaging device with a semiconductor layer that includes a photoelectric conversion unit, penetrating vias, and connecting wiring lines to connect the vias and surface-side connecting portions, allowing for a stacked configuration that reduces height and increases wiring speed and density, using materials like copper and aluminum for the wiring lines and cobalt for the connecting portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the device is scaled down to reduce size, then the height decreases, but the wiring speed and wiring density cannot be further increased
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional stacked wiring by introducing penetrating vias that extend vertically through the semiconductor layer. This allows wiring to occur in multiple dimensions (horizontal wiring lines plus vertical penetrating vias), enabling continued wiring speed and density improvements even as the device height is reduced through stacking.
Solution Approach 2:
The patent implements a stacked configuration where multiple semiconductor layers are nested vertically, with penetrating vias passing through multiple layers to connect corresponding connecting portions. This nested structure allows compact vertical integration while maintaining high wiring density and speed through the three-dimensional interconnect architecture.
2Length of stationary object
If the device is scaled down to reduce size, then the height decreases, but the wiring density cannot be further increased
Solution Approach 1:
The patent adds the vertical dimension to wiring architecture by introducing penetrating vias that extend through the semiconductor layer thickness. This transforms two-dimensional wiring into three-dimensional wiring, allowing increased wiring density without increasing device footprint or height, as wires are distributed across multiple vertical levels.
Solution Approach 2:
The patent segments the wiring architecture into multiple independent components: horizontal wiring lines in different layers, vertical penetrating vias connecting the layers, and connecting portions at various heights. This segmentation allows each component to be optimized independently and combined to achieve high overall wiring density in a compact stacked configuration.
3Quantity of substance
If wiring lines are arranged more densely, then the wiring density increases, but the light collection characteristics may be degraded
Solution Approach 1:
The patent moves wiring structures into the vertical dimension through stacking and penetrating vias, separating them from the light-receiving surface plane. This spatial separation allows high wiring density in the vertical direction without blocking incident light at the surface, thereby maintaining light collection characteristics while achieving increased wiring density.
Solution Approach 2:
The patent applies different structural qualities to different regions: the light-receiving surface maintains high optical quality with minimal obstructions for optimal light collection, while the vertical bulk structure contains the dense wiring infrastructure. This local differentiation allows high wiring density without compromising surface light collection characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a further decrease in device height, an increase in wiring speed, and a higher wiring density, while allowing for easier arrangement of wiring lines and reduced chip size without degrading light collection characteristics.
Implementation Method 1
a semiconductor layer in which a photoelectric conversion unit that photoelectrically converts incident light
Data Source
AI summary
A solid-state imaging device to be provided includes a first semiconductor device including a semiconductor layer in which a photoelectric conversion unit that photoelectrically converts incident light and a penetrating via are provided, a first connecting portion and a second connecting portion on the surface side of the semiconductor layer on the side that receives the light, and a connecting wiring line that connects the first connecting portion, the second connecting portion, and the penetrating via. The solid-state imaging device further includes a second semiconductor device that is mounted on the first semiconductor device with the first connecting portion. The solid-state imaging device is connected to an external terminal by the second connecting portion.