Stacked Imaging Circuit Layout With Fewer Bonding Steps
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Solution Overview
Problem
Current imaging devices face challenges in reducing size while maintaining functionality, requiring multiple polishing and bonding steps which lowers yield and increases manufacturing costs.
Innovation Solution
A highly functional imaging device is designed with a layered structure, including read circuits, driver circuits, memory circuits, and pixel circuits, where metal oxide transistors with overlapping conductive layers are used to reduce the number of manufacturing steps and improve yield, utilizing conductive layers made of Cu, Al, or Au for efficient electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple polishing and bonding steps are performed to stack semiconductor devices, then functionality is improved, but manufacturing complexity and time increase
Solution Approach 1:
The patent combines multiple semiconductor devices (pixel circuit, memory circuit, and other functional circuits) into a single integrated chip structure, eliminating the need for multiple separate polishing and bonding steps. This merging approach maintains high functionality while significantly reducing manufacturing complexity and process time.
Solution Approach 2:
The patent utilizes three-dimensional stacking arrangement where different circuit layers are positioned at different vertical levels within the same chip. This dimensional approach allows multiple functions to coexist in a compact space without requiring sequential assembly steps, thereby reducing manufacturing complexity while maintaining versatility.
2Adaptability or versatility
If multiple polishing and bonding steps are performed to stack semiconductor devices, then functionality is improved, but manufacturing time increases
Solution Approach 1:
The patent combines multiple semiconductor devices (pixel circuit, memory circuit, and other functional circuits) into a single integrated chip structure, eliminating the need for multiple separate polishing and bonding steps. This merging approach maintains high functionality while significantly reducing manufacturing complexity and process time.
Solution Approach 2:
The patent integrates all necessary circuit components (pixel circuits, memory circuits, driver circuits) into a pre-assembled chip structure before final installation. This preliminary integration of multiple functions into a single unit eliminates the need for time-consuming sequential assembly steps during final manufacturing.
3Adaptability or versatility
If multiple polishing and bonding steps are performed to stack semiconductor devices, then functionality is improved, but yield decreases
Solution Approach 1:
The patent combines multiple semiconductor devices (pixel circuit, memory circuit, and other functional circuits) into a single integrated chip structure, eliminating the need for multiple separate polishing and bonding steps. This merging approach maintains high functionality while significantly reducing manufacturing complexity and process time.
4Volume of moving object
If device size is reduced, then integration is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes three-dimensional stacking arrangement where different circuit layers are positioned at different vertical levels within the same chip. This dimensional approach allows multiple functions to coexist in a compact space without requiring sequential assembly steps, thereby reducing manufacturing complexity while maintaining versatility.
Data Source
AI summary
One embodiment of the present invention relates to a highly functional imaging device that can be manufactured through a small number of steps. The imaging device is formed by bonding a plurality of layers or stacks each including a device to each other. A pixel circuit; a memory circuit; and a pixel driver circuit, a driver circuit of the memory circuit, and the like can be provided for a first layer, a second layer, and a third layer, respectively. With such a structure, a small imaging device can be formed. Furthermore, wiring delay or the like can be inhibited by stacking the circuits, so that a high-speed operation can be performed.