Stacked Imaging Chip Layout for Post-Bonding Pellet Check
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Solution Overview
Problem
The existing chip on wafer (CoW) technology faces challenges in evaluating test patterns after chip bonding due to diced test patterns, which hinders manufacturing efficiency and increases costs when chip sizes vary, and prevents downsizing of imaging devices.
Innovation Solution
The proposed solution involves stacking a second semiconductor chip on a first semiconductor chip with their side surfaces on the same plane, allowing for the transfer and dicing of a region for pellet check, enabling evaluation after bonding while preventing chip size increase and maintaining downsizing capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If chip on wafer (CoW) technology is used to transfer and stack chips, then manufacturing flexibility and non-defective product selection are improved, but test pattern evaluation after bonding becomes impossible because the test pattern is diced before stacking
Solution Approach 1:
The test pattern is arranged in a region that will be diced along with the wafer, but the dicing is performed after the chip is stacked on the wafer. This preliminary arrangement of the test pattern in the dicing region allows evaluation to be performed after bonding, resolving the contradiction between manufacturing flexibility and test pattern evaluation capability.
2Productivity
If wafer on wafer (WoW) bonding is used to stack chips, then manufacturing efficiency is maintained, but chip size has to be adjusted to the largest chip size when individual chip sizes differ, increasing cost and reducing efficiency
Solution Approach 1:
The wafer is divided into multiple chips, and each chip can have different sizes. The chip on wafer method allows each chip to be processed and tested independently before being stacked on the final wafer, eliminating the need to adjust all chips to the largest size and enabling more efficient manufacturing of mixed-size chips.
3Measurement precision
If the test pattern region is retained on the chip after dicing, then post-bonding evaluation is enabled, but the chip size increases which hinders downsizing of imaging devices
Solution Approach 1:
The test pattern region is positioned in an area that will be removed during the dicing process. By utilizing the dimensional relationship between the chip layout and dicing lines, the test pattern serves its evaluation purpose during manufacturing while not occupying permanent space on the final chip, thus enabling post-bonding evaluation without increasing chip size.
Data Source
AI summary
The present technology relates to an imaging device, an electronic device, and a manufacturing method capable of evaluating a chip at a desired timing.The imaging device includes: a first semiconductor chip; and a second semiconductor chip stacked on the first semiconductor chip, in which at least one surface of side surfaces of the first semiconductor chip and at least one surface of side surfaces of the second semiconductor chip are on the same plane. The first semiconductor chip includes a first structure having a ring-shape, and the second semiconductor chip is disposed at a position straddling the first structure on the first semiconductor chip. The present technology can be applied to, for example, an imaging device in which a plurality of semiconductor chips is stacked.