Stacked Imaging Chip Structure With Impurity Layer for Leakage Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing the total thickness, length, and size, particularly when multiple semiconductor substrates are laminated, leading to issues such as increased wiring resistance and power consumption.
Innovation Solution
The implementation of a high-concentration impurity layer on the surface of semiconductor chips, specifically on the side opposite to the lamination surface, to prevent leakage and enable thinner chip configurations, with a thickness of 20 μm or less.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the thickness of semiconductor substrates is reduced to make devices thinner and smaller, then the overall device size is reduced, but leakage occurs due to defects in the thinned substrate
Solution Approach 1:
The patent applies local quality by forming a high-concentration impurity layer at specific locations (back surface or middle of substrate) rather than uniformly throughout. This localized modification addresses leakage at defect sites while maintaining the overall thin substrate structure, allowing the substrate to be thin yet reliable where needed
Solution Approach 2:
The high-concentration impurity layer is formed in advance during manufacturing, before the substrate is thinned or laminated. This preliminary action prevents leakage issues from developing later, as the impurity layer is already in place to block depletion layer spread from any potential defects
2Area of stationary object
If multiple semiconductor substrates are laminated to reduce chip area and wiring resistance, then device integration is improved, but the total thickness increases
Solution Approach 1:
The patent changes the thickness parameter of individual substrates by thinning them to extreme degrees (making each substrate very thin). This allows multiple substrates to be laminated while keeping the total thickness manageable, as each contributing layer is minimized in thickness
Solution Approach 2:
The patent segments the semiconductor device into multiple thin substrate layers, each performing specific functions. By dividing the device into separate laminated layers rather than using a single thick substrate, the overall structure achieves better integration while the thinning of individual layers controls the total thickness
3Volume of moving object
If the substrate is thinned to reduce device size, then the device becomes smaller, but defects in the thinned substrate cause leakage
Solution Approach 1:
The patent converts the potential harm of defects into a benefit by strategically placing high-concentration impurity layers that proactively block leakage paths. Instead of trying to eliminate all defects (which is difficult in thinned substrates), the impurity layers work with the defects already present, blocking depletion layer spread from defect sites and turning the defective thinned structure into a reliable device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the thickness of semiconductor chips to 20 μm or less, minimizing leakage and preventing defective products, thereby achieving a shorter and smaller device design.
Implementation Method 1
forming a high-concentration impurity layer on the surface or side surfaces of the semiconductor chips to prevent leakage by blocking the spread of depletion layers and defects
Data Source
AI summary
The present technology relates to an imaging element and a semiconductor chip that enable the imaging element to be shorter. A first chip including a photodiode, and a second chip including a circuit configured to process a signal from the photodiode are laminated, and an impurity layer is provided on a second surface opposite to a first surface of the second chip on which the first chip is laminated. The impurity layer is formed to have an impurity concentration higher than an impurity concentration of a semiconductor substrate constituting the second chip. In the present technology, for example, an imaging element that is configured by laminating a plurality of chips and is shorter and smaller can be applied.