Stacked Imaging Element Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
In three-dimensionally structured imaging and semiconductor elements, the increased length of wiring lines between stacked substrates can lead to higher parasitic capacitance, deteriorating efficient conversion and signal processing.
Innovation Solution
The implementation of an amplification transistor with a channel region, source region, and drain region in a plane intersecting the substrate surface, along with a gate electrode opposed to the channel region with a gate insulating film, reduces wiring line length and parasitic capacitance by allowing direct electrical coupling between the transistors and charge-holding sections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensionally structured imaging element with stacked substrates is used to achieve higher pixel density, then pixel density is improved, but wiring line length increases leading to higher parasitic capacitance
Solution Approach 1:
The gate electrode is configured to extend in the thickness direction of the substrate, transitioning from a planar two-dimensional structure to a three-dimensional vertical structure. This dimensional change allows the gate electrode to directly contact the charge-holding section through the substrate thickness, eliminating the need for long lateral wiring lines and thereby reducing parasitic capacitance while maintaining high pixel density
2Device complexity
If wiring lines are used to couple stacked substrates, then substrate stacking is achieved, but wiring line length increases causing signal degradation
Solution Approach 1:
The gate electrode and the charge-holding section are merged into a single integrated structure where the gate electrode extends through the substrate thickness to directly contact the charge-holding section. This merging eliminates the need for separate wiring lines to couple the amplification transistor and charge-holding section, thereby reducing signal degradation while maintaining substrate stacking complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses the decrease in efficient conversion and noise, enhancing the imaging and semiconductor element's performance by reducing parasitic capacitance and on-resistance while maintaining high pixel density.
Implementation Method 1
The first semiconductor substrate includes a photoelectric conversion section
Data Source
AI summary
An imaging element according to an embodiment of the present disclosure includes a first semiconductor substrate, and a second semiconductor substrate stacked over the first semiconductor substrate with an insulating layer interposed therebetween. The first semiconductor substrate includes a photoelectric conversion section, and a charge-holding section that holds charges transferred from the photoelectric conversion section. The second semiconductor substrate includes an amplification transistor that generates a signal of a voltage corresponding to a level of charges held in the charge-holding section. The amplification transistor includes a channel region, a source region, and a drain region in a plane intersecting a front surface of the second semiconductor substrate, and includes a gate electrode being opposed to the channel region with a gate insulating film interposed therebetween and being electrically coupled to the charge-holding section.