Stacked Imaging Device Pixel Circuits for High-Speed Low-Power Processing
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Solution Overview
Problem
Existing imaging devices struggle to integrate advanced functions such as image processing while maintaining high speed, low power consumption, and a compact form factor.
Innovation Solution
The proposed imaging device incorporates a multi-layered structure with pixel blocks that include pixel circuits, memory circuits, product-sum operation circuits, and binarization circuits, all of which utilize transistors with metal oxide channels for low off-state current and high reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If image processing functions are added to the imaging device, then user convenience and intelligence are improved, but device area and complexity increase
Solution Approach 1:
The patent applies stacking technology to arrange pixel circuits and image processing circuits in different layers (first layer and second layer). This vertical arrangement allows multiple functions to be integrated without increasing the planar area, effectively resolving the contradiction between adding image processing functions and maintaining a compact device footprint.
Solution Approach 2:
The patent integrates image processing circuits within the pixel block structure, nesting processing functions inside the imaging unit. This allows the processing circuits to share the same physical space as the pixel circuits through vertical stacking, reducing overall device area while maintaining full functionality.
2Productivity
If processing is performed externally, then device complexity is reduced, but communication speed and user convenience deteriorate
Solution Approach 1:
The patent merges the image processing circuits with the pixel circuits by stacking them in the same pixel block. This integration eliminates the need for external communication interfaces and data transmission, allowing processing to occur directly within the imaging device and significantly improving communication speed and responsiveness.
3Adaptability or versatility
If more circuits are added, then functionality is improved, but power consumption increases
Solution Approach 1:
By stacking circuits in vertical layers, the patent reduces wiring lengths between pixel circuits and processing circuits. This shortened interconnection reduces parasitic resistance and capacitance, thereby reducing dynamic power consumption while maintaining enhanced functionality.
4Speed
If wiring length is increased, then device area is reduced, but operation speed and power consumption deteriorate
Solution Approach 1:
The patent uses vertical stacking to place pixel circuits and processing circuits close to each other in the vertical dimension. This three-dimensional arrangement dramatically shortens the wiring length between circuits compared to planar arrangements, enabling high-speed operation while maintaining a compact footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high-speed image processing with reduced power consumption, allowing for a small, advanced imaging device with improved user convenience and reduced peripheral load.
Implementation Method 1
a transistor including a metal oxide in a channel formation region
Data Source
AI summary
An imaging device that has an image processing function and is capable of operating at high speed is provided. The imaging device has an additional function such as image processing, image data obtained by an imaging operation is binarized in a pixel unit, and a product-sum operation is performed using the binarized data. A memory circuit is provided in the pixel unit and retains a weight coefficient used for the product-sum operation. Thus, an arithmetic operation can be performed without the weight coefficient read from the outside every time, whereby power consumption can be reduced. Furthermore, a pixel circuit, a memory circuit, and the like and a product-sum operation circuit and the like are stacked, so that the lengths of wirings between the circuits can be reduced, and high-speed operation with low power consumption can be performed.