Stacked Solid-State Imaging Device Pixel Control Circuit Arrangement
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Solution Overview
Problem
The challenge in solid-state imaging devices is the increased chip area and size due to the integration of column signal processing circuits, which hinders the reduction of the device's size, especially when trying to minimize the projection area while maintaining efficient pixel control and signal processing.
Innovation Solution
A stacked solid-state imaging device configuration where the pixel array unit is on one semiconductor substrate, and the pixel control circuit and reading circuit are on a second substrate, with connection electrodes arranging all circuit elements within the pixel immediate region, allowing for efficient signal transfer and reduced area usage by wiring pixel control signals along the row and column directions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If column signal processing circuits are integrated for each column of the pixel array unit, then signal processing efficiency is improved, but chip area and device size increase
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration. The pixel array unit is placed on a first substrate while column signal processing circuits are arranged on a second substrate in a region overlapping the pixel array unit's projection area. This vertical stacking enables efficient signal processing while reducing the horizontal chip area occupied by these circuits.
Solution Approach 2:
The patent implements a nested arrangement where the projection area of the column signal processing circuits on the second substrate overlaps with and is contained within the projection area of the pixel array unit on the first substrate. This nesting allows the processing circuits to be positioned directly below the pixel array, minimizing the overall device footprint while maintaining full signal processing capability.
2Measurement precision
If the number of pixels is increased, then imaging resolution is improved, but chip area and device size increase
Solution Approach 1:
By arranging column signal processing circuits on a separate substrate in the vertical dimension, the patent frees up horizontal space on the first substrate. This allows for an increased number of pixels to be packed into the pixel array unit without proportionally increasing the overall chip area, thereby improving imaging resolution while controlling device size.
Solution Approach 2:
The patent segments the device into distinct functional layers: the pixel array unit on the first substrate and the column signal processing circuits on the second substrate. This segmentation allows independent optimization of each component - the pixel array can be maximized for resolution while the processing circuits occupy the vertical space, reducing the horizontal footprint.
3Device complexity
If peripheral circuits are arranged around the pixel array unit in a monolithic structure, then device integration is improved, but projection area increases
Solution Approach 1:
The patent moves peripheral circuits (column signal processing circuits) from the horizontal plane to the vertical dimension by placing them on a second substrate stacked on the first substrate. This allows the circuits to be positioned in a region overlapping the pixel array unit's projection area, maintaining high device integration while minimizing the overall projection area of the solid-state imaging device.
Solution Approach 2:
The patent extracts the column signal processing circuits from the pixel array unit's immediate vicinity on the same substrate and relocates them to a separate second substrate. This extraction allows the pixel array unit to maintain a compact form factor while the processing circuits are positioned in the vertical space, reducing the horizontal projection area without sacrificing integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the projection area of the solid-state imaging device to the size of the pixel array unit, improving signal processing efficiency and reliability by optimizing the arrangement of circuit elements and signal lines.
Implementation Method 1
a pixel array unit in which a plurality of pixels configured to convert incident light into pixel signals are arranged
Data Source
AI summary
A solid-state imaging device includes a first semiconductor substrate including a pixel array unit, a second semiconductor substrate stacked on a surface of a side opposite to a side on which light is incident in the first semiconductor substrate and on which a pixel control circuit and a reading circuit are arranged, and a plurality of connection electrodes configured to electrically connect pixel control signal lines between the first semiconductor substrate and the second semiconductor substrate, wherein the connection electrodes electrically connect pixel control signal lines within a pixel immediate region which overlaps a region where the pixel array unit is arranged in the first semiconductor substrate, and the pixel control circuit is arranged along an edge of the pixels in either one of a row direction and a column direction arranged in the pixel array unit in the pixel immediate region.