3D Stacked Imaging Element Layout for Smaller Pixels
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Solution Overview
Problem
In imaging elements with a three-dimensional configuration, stacking three semiconductor chips while maintaining a reduced chip size and pixel area is challenging, as it is difficult to bond the front surfaces of all semiconductor substrates effectively, leading to potential increases in chip size or impairment of pixel area reduction.
Innovation Solution
The imaging element comprises three substrates stacked in order, with each substrate containing specific semiconductor components: the first substrate includes sensor pixels for photoelectric conversion, the second substrate includes a readout circuit for processing pixel signals, and the third substrate includes a logic circuit for further signal processing. Electrical coupling between the substrates is achieved through a combination of interlayer insulating films, through wiring lines, and pad electrodes, allowing for flexible layout and reduced chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If three semiconductor substrates are stacked planlessly, then the chip size increases, but the area per pixel reduction is impaired
Solution Approach 1:
The imaging element is divided into three separate semiconductor substrates stacked in a specific order: first substrate with sensor pixels, second substrate with readout circuits, and third substrate with logic circuits. This segmentation allows each substrate to be optimized independently for its specific function while maintaining overall compactness, preventing chip size increase despite the three-layer configuration.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration with specific vertical layering. By arranging substrates in the vertical dimension with sensor pixels on the first substrate, readout circuits on the second substrate, and logic circuits on the third substrate, the design achieves higher integration density without increasing the horizontal chip footprint, thus preserving area per pixel reduction.
2Device complexity
If three semiconductor chips are stacked, then the electrical coupling complexity increases, but the chip size reduction is compromised
Solution Approach 1:
Bonding pads are introduced as intermediary elements between the three semiconductor substrates to facilitate electrical coupling. The bonding pads are strategically positioned on the second substrate to enable direct electrical connection between the first substrate (sensor pixels), second substrate (readout circuits), and third substrate (logic circuits). This intermediary approach simplifies the electrical coupling architecture compared to direct through-substrate connections, reducing overall system complexity while maintaining compact chip dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables further reduction in chip size and pixel area while maintaining effective electrical coupling between the substrates, allowing for expanded areas for readout and logic circuits without increasing chip size, thus preserving the reduction in area per pixel.
Implementation Method 1
The first substrate includes, in a first semiconductor substrate, a sensor pixel performing photoelectric conversion
Data Source
AI summary
An imaging element according to an embodiment of the present disclosure includes: a first substrate, a second substrate, and a third substrate that are stacked in this order. The first substrate including a sensor pixel that performs photoelectric conversion and the second substrate including a readout circuit are electrically coupled to each other by a first through wiring line provided in an interlayer insulating film. The second substrate and the third substrate including a logic circuit are electrically coupled to each other by a junction between pad electrodes or a second through wiring line penetrating through a semiconductor substrate.