Stacked Imaging Element Polishing Layout for Bonding Reliability

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The reliability of stacked imaging devices is compromised due to defects during manufacturing, primarily caused by excessive polishing of semiconductor substrates, which can lead to contamination and bonding failures.

Innovation Solution

Incorporating a polishing adjustment section with a lower polishing rate material, such as silicon nitride or silicon oxide, in the peripheral regions of the semiconductor elements to prevent excessive polishing and ensure even surface flatness during the manufacturing process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the semiconductor substrate is polished to improve surface flatness, then bonding reliability is improved, but excessive polishing causes contamination and defects

Engineering Contradiction:
Improvesurface flatnessVSAvoidbonding reliability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The polishing adjustment section is provided only in the peripheral region of the semiconductor substrate, not in the entire substrate. This local modification allows the peripheral area to be polished at a different rate than the central wiring region, preventing excessive polishing at edges while maintaining overall surface flatness and avoiding contamination

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The polishing adjustment section is formed in advance before the bonding process. By pre-forming this section with material having different polishing characteristics, the substrate is prepared to resist excessive polishing during subsequent manufacturing steps, preventing contamination before it can occur

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If the polishing process is extended to ensure even flatness, then surface quality is improved, but manufacturing time and risk of defects increase

Engineering Contradiction:
Improvesurface flatnessVSAvoidmanufacturing time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

By localizing the polishing adjustment section to the peripheral region, the polishing process can be optimized to focus on achieving flatness without requiring extended polishing time across the entire substrate. The adjusted section controls the polishing rate locally, enabling faster overall processing while maintaining surface quality

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively suppresses excessive polishing and contamination, enhancing the reliability and quality of the imaging device by maintaining flatness and preventing bonding failures, thus reducing defects during manufacture.

Implementation Method 1

a polishing adjustment section including a material that is lower in polishing rate than a constituent material of the semiconductor substrate

Methodology Applied
Scientific EffectDifferential polishing rate: Wear

Data Source

PatentUS11862662B2Image device
Publication Date: 2024.01.02 SONY SEMICON SOLUTIONS CORP
  • US11862662B2 patent drawing
  • US11862662B2 patent drawing
  • US11862662B2 patent drawing

AI summary

Provided is an imaging device (1) including: an imaging element (10); and a semiconductor element (20, 30) provided to be opposed to the imaging element and electrically coupled to the imaging element. The semiconductor element includes: a wiring region (20A, 30A) provided in a middle portion and a peripheral region (20B, 30B) outside the wiring region; a wiring layer (22, 32) having a wiring line in the wiring region; a semiconductor substrate (21, 31) opposed to the imaging element with the wiring layer interposed therebetween and having a first surface (Sa, Sc) and a second surface (Sb, Sd) in order from a side of the wiring layer; and a polishing adjustment section (23, 33) including a material that is lower in polishing rate than a constituent material of the semiconductor substrate, the polishing adjustment section being disposed in at least a portion of the peripheral region and provided in a thickness direction of the semiconductor substrate from the second surface.