Stacked Imaging Sensor with Column ADC for Area Reduction
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Solution Overview
Problem
Conventional imaging sensors with column-parallel A/D converters face increased area requirements and heat generation issues due to the need for interconnections and independent operation of ADCs, which affects the size and efficiency of the imaging sensor.
Innovation Solution
A stacked imaging sensor design where a signal processing chip is provided for one or more pixel columns or rows, featuring a readout unit and signal processing units that perform parallel signal processing, reducing heat generation and area usage by arranging ADCs in a two-dimensional layout on the signal processing chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a column-parallel ADC is formed on the same plane with the effective pixel area, then signal processing can be performed in parallel for each pixel column, but the area of the imaging sensor increases
Solution Approach 1:
The patent moves the ADC from the two-dimensional plane of the imaging chip to a stacked three-dimensional configuration on a separate signal processing chip. This vertical dimensionality change allows parallel signal processing while eliminating the area occupation on the imaging sensor plane, resolving the contradiction between processing capability and sensor area.
Solution Approach 2:
The patent divides the imaging system into two separate functional chips: an imaging chip for pixel signal generation and a signal processing chip for ADC conversion. This segmentation allows each chip to be optimized independently, enabling parallel processing on the signal processing chip without increasing the imaging sensor area.
2Speed
If multiple rows are subjected to parallel/high speed processing, then processing speed increases, but interconnections have to be routed in the effective pixel area increasing complexity
Solution Approach 1:
By moving signal processing to a stacked chip, the patent eliminates the need for complex lateral interconnections across the effective pixel area. Connections are made vertically through the stack, simplifying the interconnection architecture while maintaining high-speed parallel processing capability.
3Productivity
If the size of ADC becomes large to handle multiple rows in parallel, then processing capability improves, but the area of the imaging sensor further increases
Solution Approach 1:
The patent resolves this contradiction by placing the large ADC on a stacked signal processing chip rather than on the imaging chip plane. This allows the ADC to be large enough to handle multiple rows in parallel without occupying imaging sensor area, as the two components exist in different spatial layers.
4Productivity
If a block-parallel ADC is used with independent operation for each block, then signal processing is distributed, but each ADC generates heat independently causing local heat generation in the signal processing chip
Solution Approach 1:
The patent merges multiple block-parallel ADCs into a unified column-parallel ADC architecture where all pixel columns from all blocks are processed by a single ADC. This consolidation reduces the number of independently operating ADCs, thereby reducing local heat generation points while maintaining distributed processing capability through the column-parallel structure.
Data Source
AI summary
An imaging sensor comprising: an imaging chip in which a plurality of pixel are arranged in a matrix; and a signal processing chip that is each provided for one or more pixel columns or one or more pixel rows, has a device that performs signal processing on a pixel signal output from a pixel, and is stacked with the imaging chip is provided. For example, the device that performs signal processing is an A/D converter that converts a pixel signal output from the pixel into a digital signal, and when a pixel signal output from the pixel is converted into a digital signal, at least two or more A/D converters among the A/D converters are controlled in parallel.