Stacked Imaging Element Layout for Smaller Substrate Footprint
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Solution Overview
Problem
Conventional imaging elements face challenges in downsizing due to the need for contact regions between stacked substrates, which increases the substrate area.
Innovation Solution
An imaging element configuration where a first semiconductor substrate with a photoelectric conversion section is stacked on the back surface of a second semiconductor substrate, which includes a pixel circuit and a high impurity concentration region connected to the first substrate for shared reference potential, reducing the area required for contact regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact regions are provided between stacked substrates for shared reference potential, then electrical connection is achieved, but substrate area increases
Solution Approach 1:
The patent transitions from planar contact regions to vertical through-substrate conductors. The reference potential conductor penetrates the substrate thickness direction, establishing electrical connection between first and second substrates without requiring lateral contact regions. This dimensional change from 2D to 3D connectivity resolves the area expansion problem while maintaining reliable electrical connection for reference potential sharing.
Solution Approach 2:
The through-substrate reference potential conductor is nested within the substrate structure, passing through the substrate thickness and integrating with the stacked substrate configuration. This nesting approach allows the conductor to occupy minimal lateral space while establishing continuous electrical connection across multiple substrate layers, thereby avoiding area increase.
2Ease of manufacture
If circuits having different characteristics are disposed on different substrates, then manufacturing flexibility is improved, but device complexity increases
Solution Approach 1:
The patent divides the imaging device into functionally independent substrate layers: first substrate for photoelectric conversion elements, second substrate for pixel circuits, and third substrate for signal processing circuits. Each substrate can be manufactured using optimized processes for its specific circuit type, then stacked together. This segmentation enables manufacturing flexibility while the systematic stacking approach manages complexity through modular integration.
Solution Approach 2:
The stacked substrate configuration serves multiple functions simultaneously: enabling separate manufacturing optimization for different circuit types, providing mechanical support structure, establishing electrical connections through through-substrate conductors, and facilitating heat dissipation. This multi-functionality justifies the increased structural complexity by delivering manifold benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a more compact imaging element design by minimizing the area needed for contact regions, enabling downsizing while maintaining effective signal processing and reference potential usage.
Implementation Method 1
a photoelectric conversion section that performs photoelectric conversion of incident light
Data Source
AI summary
To downsize an imaging element formed by stacking a plurality of semiconductor substrates. The imaging element includes a first semiconductor substrate and a second semiconductor substrate. The first semiconductor substrate includes a photoelectric conversion section that performs photoelectric conversion of incident light. The second semiconductor substrate includes a pixel circuit that generates an image signal according to a charge generated by the photoelectric conversion, an element isolating region that isolates elements of the pixel circuit, and a high impurity concentration region which is disposed below the element isolating region and having a high impurity concentration and is connected to the first semiconductor substrate in order to use a reference potential in common, with the first semiconductor substrate being stacked on a back surface side of the second semiconductor substrate.