Stacked Semi-Circular On-Chip Inductor for Q and Area Limits
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Solution Overview
Problem
The existing on-chip inductor structures in semiconductor integrated circuits have a reduced quality factor (Q value) due to thinner inductor traces, which affects the performance of integrated circuit devices.
Innovation Solution
A multilayer-type on-chip inductor structure is designed with a first and second winding portion in the inter-metal dielectric (IMD) layer, each comprising semi-circular stacking layers and input/output conductive portions. A conductive branch layer is also included in the insulating redistribution layer, electrically coupled to the semi-circular stacking layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If thinner inductor traces are used in digital or baseband circuit process, then manufacturing cost is reduced, but quality factor (Q value) is reduced
Solution Approach 1:
The patent transitions from planar 2D inductor traces to a 3D multilayer stacked structure. Multiple semi-circular stacking layers are vertically stacked in the inter-metal dielectric layer, creating a three-dimensional configuration that increases the effective conductor cross-sectional area without increasing the planar footprint. This dimensional change allows thinner individual traces to achieve equivalent or superior electrical performance through vertical stacking.
Solution Approach 2:
The patent employs a composite structure combining multiple conductive layers (first and second semi-circular stacking layers) with insulating materials (inter-metal dielectric layer). This composite approach creates an equivalent thick trace effect by stacking multiple thinner conductive layers separated by dielectric materials, thereby maintaining low manufacturing cost while achieving high quality factor through increased effective conductor area.
2Reliability
If thicker inductor traces are used to increase quality factor (Q value), then inductor performance is improved, but manufacturing cost increases
Solution Approach 1:
Instead of using thicker traces in the planar dimension which would increase manufacturing complexity and cost, the patent achieves the equivalent electrical effect by stacking multiple thinner trace layers vertically. This creates a three-dimensional conductor structure that provides the same or greater effective cross-sectional area for current flow without requiring thicker individual traces or additional expensive RF process steps.
Solution Approach 2:
The patent divides a single thick trace into multiple thinner semi-circular stacking layers that are vertically stacked. Each layer is formed using standard digital/baseband circuit process capabilities, and the stacked configuration collectively provides the electrical performance equivalent to a much thicker trace, thereby achieving high quality factor without incurring the cost of thick-trace RF process technology.
3Ease of manufacture
If conventional planar inductor structure is used, then manufacturing is simple, but inductor area is large
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple semi-circular layers within the inter-metal dielectric layer. This vertical stacking concentrates the inductor structure in the Z-direction (thickness direction) rather than expanding it in the XY-plane, thereby achieving high inductance values and quality factors within a compact planar footprint while maintaining compatibility with standard planar fabrication processes.
Solution Approach 2:
The patent implements a nested configuration where multiple semi-circular stacking layers are concentrically arranged and vertically stacked. The first and second semi-circular stacking layers are positioned concentrically with respect to each other, creating a compact nested structure that maximizes the use of vertical space and achieves high inductance density within a minimal planar area.
Data Source
AI summary
A multilayer-type on-chip inductor includes a first winding portion arranged in an inter-metal dielectric (IMD) layer, which includes first and second semi-circular stacking layers arranged from inside to outside and in concentricity. A second winding portion includes third and fourth semi-circular stacking layers arranged symmetrically with the first semi-circular stacking layer and the second semi-circular stacking layer, respectively, with respect to a symmetry axis. A conductive branch layer is disposed in an insulating redistribution layer over the IMD layer. The first, second, third, and fourth semi-circular stacking layers each include an uppermost trace layer and a next uppermost trace layer vertically stacked under the uppermost trace layer.