Stacked Inductor-Capacitor Layout for High-Q Miniature Components
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Solution Overview
Problem
Existing electronic components with inductors and capacitors face challenges in achieving high Q values while maintaining a small size, leading to low volumetric efficiency and increased component size, which limits the effectiveness of Q value improvements in devices with limited external dimensions.
Innovation Solution
The design involves a structure with a first and second insulator layer, where a first conductor pattern and electrode pattern form an inductor and capacitor, respectively, and a second conductor pattern is electrically connected to the first along the first conductor pattern, enhancing the occupancy rate of conductors and maintaining high Q values without decreasing capacitor electrode efficiency, and a method of manufacturing that simultaneously forms these patterns on separate layers to reduce manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inductors are connected in parallel to improve Q values, then the Q value of the inductor is improved, but the volumetric efficiency of the inductor becomes low
Solution Approach 1:
The patent transitions from a planar conductor arrangement to a three-dimensional stacked configuration. Multiple conductor patterns are formed on different insulator layers (first insulator layer and second insulator layer), utilizing the vertical dimension to increase conductor occupancy rate without expanding the horizontal footprint. This dimensional transition enables high Q values while maintaining small component size.
Solution Approach 2:
The patent implements a nested structure where conductor patterns and electrode patterns are embedded within multiple insulator layers. The first conductor pattern and second conductor pattern are positioned on different layers, with insulator layers nested between them. This nested arrangement maximizes the use of available space, increasing conductor occupancy rate while keeping the overall component volume small.
2Reliability
If the size of the electronic component is increased to obtain inductors with high Q values, then the Q value of the inductor is improved, but the electronic component size is increased
Solution Approach 1:
The patent utilizes the vertical dimension by stacking conductor patterns and electrode patterns on multiple insulator layers. This three-dimensional arrangement increases the effective conductor length and occupancy rate without increasing the horizontal dimensions of the component, thereby achieving high Q values while maintaining a compact footprint suitable for limited external sizes.
Solution Approach 2:
The patent combines the formation of multiple conductor patterns and electrode patterns into a single integrated multilayer structure. The first conductor pattern, second conductor pattern, first electrode pattern, and second electrode pattern are all merged into one compact electronic component with a unified structure, maximizing space utilization and achieving high Q values without increasing overall component size.
3Reliability
If conductor layers for forming an inductor formed on different layers are connected in parallel to each other, then the Q value of the inductor is improved, but the occupancy rate of the conductors of the inductor per unit volume becomes low
Solution Approach 1:
The patent addresses the low occupancy rate by transitioning from a two-dimensional parallel connection to a three-dimensional stacked configuration. Conductor patterns on different insulator layers are vertically aligned and connected, utilizing the vertical dimension to increase the density of conductors per unit volume. This enables high Q values through parallel connection while maintaining high conductor occupancy rate.
Solution Approach 2:
The patent implements a nested arrangement where conductor patterns are embedded within insulator layers in a stacked configuration. The first conductor pattern is nested within the first insulator layer, and the second conductor pattern is nested within the second insulator layer, with the layers positioned vertically one above the other. This nested structure maximizes the occupancy rate of conductors per unit volume while enabling parallel connection for high Q values.
Data Source
AI summary
An electronic component includes a first insulator layer including thereon a first conductor pattern to define an inductor and a first electrode pattern to define a capacitor, and a second insulator layer including thereon a second conductor pattern to define the inductor and a second electrode pattern to define the capacitor. The first and second electrode patterns face each other across the second insulator layer to define the capacitor, and the second conductor pattern is electrically connected to the first conductor pattern along the first conductor pattern.