Vertical Stacked Inductor Capacitor Package for Voltage Ripple
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Solution Overview
Problem
Current voltage regulators face challenges in mitigating output voltage ripple, overshoot, and input PDN impedance, particularly in smaller integrated circuit packages, where existing solutions either require large inductors or complex active clamp circuitry, increasing complexity and cost.
Innovation Solution
The proposed solution involves vertically stacking inductors and capacitors above or below the electronics package, with insulated capacitors connected to magnetic inductors via pillars, allowing for effective output voltage ripple and transient mitigation without increasing package size, and decoupling capacitance from the die to address topology differences across product lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If large inductors are used to mitigate voltage ripple, then voltage ripple is reduced, but package area increases and transient load performance deteriorates
Solution Approach 1:
The patent transitions from planar inductor placement to three-dimensional vertical stacking, positioning inductors above or below the package substrate. This dimensional change allows ripple mitigation functionality without consuming additional package footprint area, directly resolving the contradiction between voltage ripple reduction and package area constraints.
Solution Approach 2:
The patent embeds inductors within the package structure by stacking them vertically on top of or beneath the substrate, effectively nesting the inductor components within the existing package volume. This nesting approach provides ripple mitigation while maintaining a compact package footprint.
2Object-affected harmful factors
If large inductors are used to mitigate voltage ripple, then voltage ripple is reduced, but transient load performance worsens
Solution Approach 1:
The patent employs multiple smaller inductors with different characteristics distributed across the vertical stacking structure, rather than a single large inductor. This local differentiation allows optimization of transient response while maintaining ripple mitigation, as each inductor can be tuned for specific performance aspects.
3Object-affected harmful factors
If re-partitioning at full chip level is used to mitigate voltage ripple, then voltage ripple is reduced, but design complexity increases
Solution Approach 1:
The patent extracts the ripple mitigation function from the complex full-chip re-partitioning approach and implements it through a standardized vertical stacking module. This extraction simplifies the design process by providing a pre-configured solution that can be integrated without extensive redesign of the entire chip architecture.
4Object-affected harmful factors
If complex active clamp circuitry is used to mitigate voltage overshoot, then voltage overshoot is limited, but device complexity increases
Solution Approach 1:
The patent uses the vertical stacking configuration to inherently limit voltage overshoot by controlling the inductance values and their arrangement, converting what would require complex active circuitry into a passive structural solution. The physical arrangement of inductors in the vertical stack provides natural overshoot mitigation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces voltage ripple and overshoot, mitigates input PDN impedance, and provides additional capacitance for load transients, enabling smaller package sizes and reduced complexity while maintaining performance.
Implementation Method 1
one or more magnetic inductors; vertically stacking inductors and capacitors above or below the electronics package
Implementation Method 2
one or more capacitors positioned one of above or below to the one or more magnetic inductors
Data Source
AI summary
Apparatuses and methods including an apparatus for an electronics package are disclosed. According to one embodiment, the apparatus can include one or more magnetic inductors, one or more capacitors positioned one of above or below to the one or more magnetic inductors and a plurality of electrical conductors comprising pillars. The pillars can extend substantially vertically to electrically connect the one or more magnetic inductors and the one or more capacitors to the electronics package and the one or more magnetic inductors, the one or more capacitors and the plurality of conductors are disposed one of above or below the electronics package; and at least one electrical conductor comprising a pillar extending substantially vertically to electrically connect the one or more magnetic inductors and the one or more capacitors.